LG 55G2 - Page 60

CPU
xi_main
1 Ghz
DDR3PLL
xo_main
1.6Ghz
DDR3PLL1
1.6Ghz
24Mhz
DDR3PLL2
0 1 0 10 1
CT
R
1/2
1/5
1.6Ghz
1.6Ghz
Memory Controller
Memory Controller
Memory Controller
800Mhz
800Mhz
Video/Audio Block
CPU peripherial
dcoin_clk
DCO
DCO
200Mhz
200Mhz
Glitch-free logic
between
de_dco_out and
sdec_dco_out
de_dco_out
sdec_dco_out
0 1
CT
R
DISPLL
u_DPLL
udnt_buf_dpll_fin
disp_fout
Clock Divide & Reset
generation w/ test logic
DE
TE
sclk
27Mhz
27Mhz
27Mhz
27Mhz
2 port USB PHY
1 port USB PHY
30/48Mhz
30/48 Mhz
i_core800_clk
i_core320_clk
i_m01_ddrclk
i_m2_ddrclk
u_crg
Clock Divide & Reset generation
w/ test logic
Clock Divide & Reset generation
w/ test logic
Clock Divide & Reset generation
w/ test logic
Clock Divide & Reset generation
w/ test logic
Clock Divide & Reset generation
w/ test logic
USB controller
About 220 internally generated clocks
SSC setting
- 0xFD3001CC
- 0xFD3001D0
SSC setting
- 0xFD3001C4
- 0xFD3001D8
SSC setting
-0xFD300108
-0xFD30010C
SSC setting
- 0xFD3001D4
- 0xFD3001D8
L9 Block diagram
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