LG 55LW9500 - Page 51

Copyright © 2011 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only
DDR3 SDRAM
- 1Gbit (x16)
- 800MHz
DDR3 SDRAM
- 1Gbit (x16)
- 800MHz
DDR1_DATA[15:0]
DDR1_A[12:0]/
BA[2:0]/CLK/CKE
SPI_DO/CK/CS
SPI_DI
SPI FLASH
(4Mbit)
0X98
SPI FLASH
(4Mbit)
0X98
+1.5V
+3.3VD
LDO Regulator
(AP7173-SPG-13)
LDO Regulator
(AP7173-SPG-13)
URSA5
(0xB4)
LVDS data from
Main IC
( BCM35230 )
XTAL_IN
XTAL_OUT
X-Tal
(24.75Mhz)
+12VD
+1.26V_FRC
DC-DC Converter
(AOZ1072AI)
DC-DC Converter
(AOZ1072AI)
Quad-link LVDS(@74.25MHz)
GP3 Backend block diagram (PG)
51Pin LVDS output
41Pin LVDS output
BCM35230
+12VD
+3.3V_FRC
DC-DC Converter
(AOZ1072AI)
DC-DC Converter
(AOZ1072AI)