LG 60LB5900 - Block Diagrams; 3 D Model Block Diagram

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LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.
Only for training and service purposes
2. 3D Model
(P1101)
30P HD LVDS wafer
51P FHD LVDS wafer
(P1100)
COMP2_L/R_IN
COMP2_Y+/AV_CVBS_IN, COMP2_Pb+/Pr+
CK+/-, D0+/-, D1+/-, D2+/-_HDMI2
DDC_SCL/SDA_2, HDMI_CEC
Serial Flash
(8Mbit)
IC1300
SPI_SCK/SDI/SDO/CS
System EEPROM
(256Kbit)
IC104
I2C_SCL/SDA
NAND FLASH
(1Gbit)
IC102
PCM_A[0-7],…
< FHD >
RXA0+/-~RXA4+/-, RXACK+/-
RXB0+/-~RXB4+/-, RXBCK+/-
SPK_R
SPK_L
AMP_SCL/SDA
AUD_MASTER_CLK,
AUD_LRCH,
AUD_LRCK, AUD_SCK
TAS5733
(IC5600)
Main SOC
M1A -128MB ⇨㣙
(IC101)
Connector
(P600)
KEY1/2, LED_R, IR
REAR
HDMI1
(JK801)
TU_SCL / SDA
SIF
D_IF
CVBS
Comp1 & AV1
(JK1701)
SPDIF_OUT
SPDIF(Optic)
(JK1001)
SIDE
USB
(JK700)
HDMI2(MHL)
(JK803)
CK+/-, D0+/-, D1+/-, D2+/-,_HDMI4, DDC_SCL/SDA_4, HDMI_CEC
SIDE_USB_DM/DP
USB1_OCD/CTL
TPS65282
+5V_USB
MHL_CD_SENSE
HP_L/ROUT, SIDE_HP_MUTE
Headphone
(JK1500)
< HD >
RXA0+/-~RXA3+/-, RXACK+/-
DDR3 SDRAM
(1Gbit)
IC1201
B-MDQL[0-7], B-MDQU[0-7],…
DDR CLK (Max) : 792 MHz