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LG 65UG8709 - URSA9 Configuration and Debugging; URSA Reset and SPI Flash

LG 65UG8709
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THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FIRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFACTURES SPECIFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
URSA_RESET
R13209
100K
+3.3V_NORMAL
R1927
0
R13223
33
URSA9_PQ_DEBUG
R1991
10K
R132001 33
URSA_L/D_ctrl
FRC_FLASH_SEL
R1930
0
OPT
I2C_SCL7
C1916 0.01uF
URSA_EMI
DIM2
SPI_DO_SOC
L/D_VSYNC
URSA_OPT_1
C1905 0.01uF
URSA_EMI
+3.3V_NORMAL
R1908
10K
OPT
URSA_OPT_4
IC1902
NLASB3157DFT2G
OPT
3
B0
2
GND
4
A
1
B1
6
SELECT
5
VCC
AR13200
33
R1990
10K
R1917 10K
URSA_BIT2_1
C1904
0.01uF
25V
URSA_EMI
SPI_DI
P1905
12507WS-04L
WAFER-STRAIGHT
URSA_DEBUG_Wafer
1
2
3
4
5
R1906
10K
OPT
R13226
10K
URSA9_PQ_DEBUG
URSA_UART1_TX
URSA_OPT_0
DIV_BIT1
IC1903
NLASB3157DFT2G
OPT
3
B0
2
GND
4
A
1
B1
6
SELECT
5
VCC
SPI_DI_SOC
FRC_FLASH_WP
URSA_UART2_TX
R13224
33
URSA9_SYS_DEBUG
R13213 10K
Div_BIT1_1
XO_URSA
SDA2_+3.3V_DB
C1909 0.01uF
URSA_EMI
SCL2_+3.3V_DB
C1910
0.01uF
25V
URSA_EMI
DIV_BIT1
L/D_DI
SW1901
JTP-1127WEM
1
2
43
C1901
0.01uF
25V
URSA_EMI
FLASH_WP_URSA
URSA_UART1_RX
SPI_DO
URSA_BIT0
R1910 10K
URSA_RX_VX1
R1959
0
URSA_MP
C1903
0.01uF
25V
URSA_EMI
C1902
0.01uF
25V
URSA_EMI
R13221
0
R13222
33
URSA9_PQ_DEBUG
C1911 0.01uF
URSA_EMI
R1911
10K
LGD_Module
SPI_CK_URSA9
C1990
47pF
50V
OPT
R1907
10K
OPT
I2CS_SCL
+3.3V_NORMAL
R13205
10K
R1905
1K
OPT
SPI_CZ_URSA9
SPI_CK
P1907
12507WS-04L
URSA9_SYS_DEBUG
1
2
3
4
5
IC1900
NLASB3157DFT2G
OPT
3
B0
2
GND
4
A
1
B1
6
SELECT
5
VCC
R13203 33
URSA_L/D_ctrl
URSA_UART2_TX
SPI_DO_URSA9
SPI_CZ_URSA9
XIN_URSA
D1900
100V
1N4148W
R19260
SW1902
JS2235S
URSA_DEBUG_SW
3
2
1
4
5
6
R1915 10K
URSA_BIT1_1
R1960
0
OPT
C1906 0.01uF
URSA_EMI
R1919
10K
OPT
DIV_BIT0
R13227
10K
URSA9_SYS_DEBUG
FRC_FLASH_SEL
R13202 10K
Div_BIT0_1
SPI_DI
I2CS_SCL
R1901
10K
OPT
R1925
1M
R19000
R1922
33
URSA_DEBUG_Wafer
R1918 10K
URSA_BIT2_0
R1958
0
URSA_MP
URSA_OPT_0
+3.3V_NORMAL
XO_URSA
L/D_CLK
+3.3V_NORMAL
LOCKAn_OSD
R1916 10K
URSA_BIT1_0
R1913 10K
URSA_BIT0_1
C1912
0.01uF
25V
URSA_EMI
R13214 10K
Div_BIT1_0
R1904
33
XIN_URSA
SPI_DO_URSA9
SPI_CK_SOC
R13225
33
URSA9_SYS_DEBUG
URSA_UART1_RX
I2CS_SDA
DIM1
DIM2
SPI_DI_URSA9
+3.3V_NORMAL
FRC_FLASH_SEL
R13212 10K
Div_BIT0_0
SDA2_+3.3V_DB
URSA_UART2_RX
R13200
10K
OPT
C1913 0.01uF
URSA_EMI
+3.3V_NORMAL
R1923
10K
X1900
24MHz
4
GND_2
1
X-TAL_1
2
GND_1
3
X-TAL_2
URSA_OPT_4
IC2500
LGE7411(URSA9)
RESET
AF29
XTALO
R3
XTALI
R4
I2CS_SDA
AJ24
I2CS_SCL
AH24
I2CM_SDA
AH26
I2CM_SCL/VSYNC_LIKE1
AG24
GPIO[0][UART2_TX]
B4
GPIO[1][UART2_RX]
A4
GPIO[2][UART1_TX]
B5
GPIO[3][UART1_RX]
A5
SPI_CZ
AD28
SPI_CK
AD30
SPI_DI
AC31
SPI_DO
AD29
INT_R21/GPIO[41]
AE28
INT_R20/GPIO[42]
AE27
IRE
C4
GND_1
AC27
GND_2
AD27
NC_1
A7
NC_2
B6
NC_3
B7
NC_4
C5
NC_5
C6
NC_6
C7
NC_7
D4
NC_8
D5
NC_9
D6
NC_10
D7
NC_11
E4
NC_12
E5
NC_13
E6
NC_14
E7
NC_15
F4
NC_16
F5
NC_17
M5
NC_18
M6
NC_19
M7
NC_20
N5
NC_21
R7
NC_22
P7
NC_23
N7
NC_24
N6
I2C_HSC_SDA/VSYNC_LIKE2
AG25
I2C_HSC_SCL/VSYNC_LIKE3
AH25
SPI1_CK/PWM2/GPIO58
AH28
SPI1_DI/PWM3/GPIO59
AJ27
SPI2_CK/PWM0/GPIO56
AJ29
SPI2_DI/PWM1/GPIO57
AF27
SPI3_CK/DIM10/GPIO54
AG28
SPI3_DI/DIM11/GPIO55
AH27
SPI4_CK/DIM8/GPIO52
AG27
SPI4_DI/DIM9/GPIO53
AG26
VSYNC_LIKE/PWM5/GPIO40
AF28
DIM0/GPIO[32]
AG23
DIM1/GPIO[33]
AG20
DIM2/GPIO[34]
AH23
DIM3/GPIO[35]
AH20
DIM4/GPIO[36]
AG21
DIM5/GPIO[37]
AH22
DIM6/GPIO[38]
AG22
DIM7/GPIO[39]
AH21
GPIO43/TCON0
A3
GPIO44/TCON1
B3
GPIO45/TCON2
A2
GPIO46/TCON3
C3
GPIO47/TCON4
B2
GPIO48/TCON5
B1
GPIO49/TCON6
C2
GPIO50/TCON7
C1
GPIO[18]/TCON8
AG4
GPIO[19]/TCON9
AG5
GPIO[20]/TCON10
AH4
GPIO[21]/TCON11
AH5
GPIO[22]/TCON12
AH6
GPIO[23]/TCON13
AJ4
GPIO24/TCON14
AJ5
GPIO25/TCON15
AJ6
GPIO[4]
AH16
GPIO[5]
AG16
GPIO[6]
Y5
GPIO[7]
Y4
GPIO[8]
AB4
GPIO[9]
AB5
GPIO[10]/PWM_DIM_IN[0]
AG17
GPIO[11]/PWM_DIM_IN[1]
AH17
GPIO[12]
AG18
GPIO[13]
AJ20
GPIO[14]
AH18
GPIO[15]
AG19
GPIO[16]
AH19
GPIO[17]
AJ21
DIV_BIT0
SPI_DI_URSA9
P1906
12507WS-04L
URSA9_PQ_DEBUG
1
2
3
4
5
C1900
0.01uF
25V
URSA_EMI
R132002
33
URSA_L/D_ctrl
URSA_BIT2
I2C_SDA7
SPI_CK
FLASH_WP_URSA
+3.3V_NORMAL
R1921
33
URSA_DEBUG_Wafer
C1991
47pF
50V
OPT
URSA_UART2_RX
LOCKAn_Video
C1997
0.1uF
16V
URSA9_SYS_DEBUG
URSA9_CONNECT
C1915 0.01uF
URSA_EMI
+3.3V_NORMAL
URSA_RESET
R13204
10K
OPT
C1998
0.1uF
16V
URSA9_PQ_DEBUG
C1907 0.01uF
URSA_EMI
R19200
I2CS_SDA
+3.3V_NORMAL
Data_Format_1
R1902
10K
R1924
0
SCL2_+3.3V_DB
DIM0
R1912
10K
OS_Module
URSA_BIT1
R1914 10K
URSA_BIT0_0
URSA_RESET_MICOM
SPI_DO
R13216 10K
URSA_DEBUG
URSA_UART1_TX
URSA_BIT2
R1909 10K
URSA_RX_LVDS
C1908
0.01uF
25V
URSA_EMI
DIM1
R190310K
C1995
0.1uF
16V
DIM0
R13215 10K
URSA_RELEASE
AR13201
33
+3.3V_NORMAL
C1996
22uF
10V
OPT
URSA_BIT1
R1961
0
OPT
R1932
1K
IC1901-*1
W25Q32FVSSIG
SPI_4MB_Winbond
3
WP[IO2]
2
DO[IO1]
4
GND
1
CS
5
DI[IO0]
6
CLK
7
HOLD_OR_RESET[IO3]
8
VCC
SPI_CK_URSA9
Data_Format_0
URSA_BIT0
URSA_RESET_SoC
URSA_OPT_1
R13206
100K
C1992
5pF
50V
C1993
5pF
50V
URSA_OPT_5
URSA_OPT_6
C13201 0.01uF
URSA_EMI
R13211 10K
R13208 10K
C13200 0.01uF
URSA_EMI
R13210 10K
OPT
R13207 10K
OPT
URSA_OPT_6
URSA_OPT_5
C13202
0.01uF
25V
URSA_Noise_KR_US
C13203
0.01uF
25V
URSA_Noise_KR_US
C13206
5pF
50V
URSA_Noise_KR_US
C13204
5pF
50V
URSA_Noise_KR_US
C13205
5pF
50V
URSA_Noise_KR_US
C13002
0.01uF
URSA_Noise_KR_US
C13003
0.01uF
URSA_Noise_KR_US
C13000
0.01uF
URSA_Noise_KR_US
C13001
0.01uF
URSA_Noise_KR_US
C13004
0.01uF
URSA_Noise_KR_US
C13005
0.01uF
URSA_Noise_KR_US
IC1901
MX25L3235E
SPI_4MB_MACRONIX
3
WP/SIO2
2
SO/SIO1
4
GND
1
CS
5
SI/SIO0
6
SCLK
7
HOLD/SIO3
8
VCC
R13201-*1
0.01uF
25V
URSA_Noise_KR_US
R13200-*1
0.01uF
25V
URSA_Noise_KR_US
R1320110K
OPT
2013.12.17
BSD-14Y-UD-132-HD
1/0/1
URSA_OPT_4
Rx Interface
DIV_BIT [1/0]
1/0
0/0 NON DIVISION
Clock for URSA9
5k@120 (20lane)
URSA Reset
High : B1
0/0/0
0/1/0
Reserved
URSA9 UART1_RX
1/0/0
SPI Flash
Module Division OPT
For DFT JIG
Low : B0
0/0/1
FHD@120 (4lane)
MODULE DIVISION
UART PQ/System Debug
Tx Lane
0/1
Chip Config
Tx Lane
Debug/ISP ADDR
Debugging for URSA9
Slave (Debug Port:0XB4,ISP:0X98)
BIT [2/1/0]
0/1/1
HIGH:URSA_PRINT_OFF
Change pin from A5 to C4
1/1/1
Division Type
URSA9 Option
FHD@60 (2lane)
2 DIVISION
OLED ULTRA HD
1/1
I2C_S Port
LM14_URSA9_crystalcap
URSA9_Vx1_RX_HTPD_GPIO
LOW:URSA_PRINT_ON
8 DIVISION
Module Type
4 DIVISION
4K@120 (16lane)
Reserved1/1/0
CHIP_CONF=3’d7:111:boot from SPI Flash
CHIP_CONF:{DIM2,DIM1,DIM0}
4k@60 (8lane)
Near URSA9 on forth layer
Near URSA9 on forth layer
Near URSA9 on forth layer
Copyright © 2015 LG Electronics. Inc. All rights reserved.
Only for training and service purposes
LGE Internal Use Only

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