LG 65UH8500 - Page 27

- 27 -
LGE Internal Use Only
Copyright © LG Electronics. Inc. All rights reserved.
Only for training and service purposes
3. F16 Block Diagram
DDR[0-1]_DQ[0-15]
DDR[0-1]_A[0:14 ]/
DDR[0-1]_BA[2:0]/
DDR3 SDRAM - 1Gbit (x16) - 2133
UART_TX_0
UART_RX_1
LOCKAN_Video
A_F16_CONNECT
F16
V x1
8 lane
41P
V x1
8 lane
51P
XIN_URSA
XO_URSA
X-Tal
(24Mhz)
SPI FLASH
-64MB (x1)
MSPI_MISO_M
MSPI_MOSI_M
I2C_SDA2
I2C_SCL2
LOCKAn_IN
HTPDAn_IN
I2C_SDA_M1
I2CS_SCL_M1
LOCKAn
HTPDAn
T-CON POWER
5 Pin
PANEL_VCC
UART_RX_0
M16
Vx1 VIDEO 8Lane
Vx1 OSD 4Lane
Data_Format_1
Data_Format_0
DDR3 SDRAM - 1Gbit (x16) - 2133
DDR3 SDRAM
- 1Gbit (x16)
- 2133
I2C_S Port
4 Pin
URSA
DEBUG
Switch
I2C_SDA7
I2C_SCL7
I2CS_SCL
I2CS_SDA
SDA2_+3.3V_DB SCL2_+3.3V_DB
UART
UART_TX_1 UART_RX_1
Jig Download
UART
UART_TX_0
UART_RX_0
UART for FRC
UART for System
UART_TX_1
Data_Format_0
Data_Format_1