LG A395 - LCD Interface

3. TECHNICAL BRIEF
- 42 -
Copyright © 2013 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
3.9 LCD Interface
Copyright © 2007 LG Electronics. Inc. All right reserved.
Only for training and service purposes
LGE Internal Use Only
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MT6255 contains a versatile LCD controller which is optimized for multimedia applications. This controller
supports many types of LCD modules and contains a rich feature set to enhance the functionality. These
features are:
• Up to 800x480 at 18 bpp @ 200 MHz, 480x320 at 18 bpp @ 133 MHz
• Supports LCD format : RGB332, RGB444, RGB565, RGB666, RGB888 LCD modules.
• 4 Layers Overlay with individual color depth, window size, vertical and horizontal offset, source key,
alpha value and display rotation control(90°,180°, 270°, mirror and mirror then 90°, 180° and 270°)cc
• One Color Look-Up Table
• Three Gamma Correction Tables
For parallel LCD modules, the LCD controller can reuse external memory interface or use dedicated 16/18-bit
parallel interface to access them and 8080 type interface is supported. It can transfer the display data from the
internal SRAM or external SRAM/Flash Memory to the off-chip LCD modules.
For serial LCD modules, this interface performs parallel to serial conversion and both 8- and 9- bit serial interface
is supported. The 8-bit serial interface uses four pins – LSCE#, LSDA, LSCK and LSA0 – to enter commands and
data.
Meanwhile, the 9-bit serial interface uses three pins – LSCE#, LSDA and LSCK – for the same purpose. Data read
is not available with the serial interface and data entered must be 8 bit.
Figure 3.9.1 LCD Interface
3. TECHNICAL BRIEF
3.9 LCD Interface
43
Figure 3.9.1 LCD Interface
C322
1u
C309
1u
VIO_2V8
VIO_1V8
VA331VA332
VIO_1V8
10K
R367
C308
1u
VA328VA327
VA329
7.5pF
FL301
105
64
73
82
91
INOUT_A1 INOUT_B1
INOUT_A2 INOUT_B2
INOUT_A3 INOUT_B3
INOUT_A4 INOUT_B4
G1 G2
CN301
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
FL300
7.5pF
105
64
73
82
91
INOUT_A1 INOUT_B1
INOUT_A2 INOUT_B2
INOUT_A3 INOUT_B3
INOUT_A4 INOUT_B4
G1 G2
C305
2.2u
100KR311
DNI
R307
2
1
R312
100K
21
VIO_1V8
100KR308
VBAT
FL302
7.5pF
105
64
73
82
91
INOUT_A1 INOUT_B1
INOUT_A2 INOUT_B2
INOUT_A3 INOUT_B3
INOUT_A4 INOUT_B4
G1
G2
LCD_RS
LCD_VSYNC
LCD_ID
LCD_LED_CA1
LCD_LED_CA2
LCD_LED_CA3
LNAND_D_[00]
LNAND_D_[01]
LNAND_D_[02]
LNAND_D_[03]
LNAND_D_[04]
LNAND_D_[05]
LNAND_D_[06]
LNAND_D_[07]
LCD_WR_N
LCD_CS_N
LCD_RST_N
LCD_RD_N
Added (10/31)
Added (10/30)
IF_MODE[1:0] = 01 --> 00
D[15:0] 16 bit --> D[7:0] 8 bit mode
Changed (9/10)
Changed from D[15:8] to D[7:0]
IM0
IM1
Added (9/10)
Added (9/10)
Changed (9/10)
TIANMA LCD ID : HIGH