LG CM4520 - Block Diagrams; Overall Block Diagram

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BLOCK DIAGRAMS
1. OVERALL BLOCK DIAGRAM
BU9543KV
RF+ SERVO DSP
IM
P/UP
M
DECK MECHANISM
AUK
S3050
A,B,C,D,E,F
PD
LD
CD_DIN_DOUT
CD_MCK/ CD_R/W
BUSY; CD-16M
SUBSYQ;
9543-RST;
341S2164
SDRAM
W25Q80BVSSIG
FLASH
MX25LB005BMC
CS5346
ADC(6CH)
AMP
TAS5612L
DMA[0..11],DB[0..15]
DSCK#,CKE,CS0#,RAS0#
SLED
s
s
,F
s
,T
s
SPINDLE
s
LOAD
s
TDO
SLDO
SPDO
FDO
12MHZ
16.93MHZ
MLC9800
MCS LOGIC
RESET; M
UTE
VFD DRIVER
ET6315
AUX
DAT, CLK, RST, CE, INT
RST, WEN#,CE#
A[0.. 18], DB[0..15]
OP/CL
OP/CL LI MIT
CD-BCK/ LRCK/ DOUTA
DAC-MCLK
P-SENSE
MICOM
LC87F5M64A
PWM
PS9854
DO
STB
CLK
ADC-CLK
ADC-DAT
ADC-RST
ADC-DATA
TUNER
R/L
R/L
I2S CLK
DAC-BCK/LRCK/MCLK
DAC-DATA
12.288MHZ
PWM-RST PWM-CLK
PWM-DAT
PDN
SD; OTW
FL+
FL-
FR+
FR-
D+/-
CP-RET
R
L
EEPROM
DAT
CLK
SPI-DO/DI/CLK/ CS
RMC
KEY
9.8304MHZ
32.766khz
Standby LED
VFD
VOLUME LED
D+/-
USB1
USB2
USB
HUB IC
D+/-
CP-SDA/SCL