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3. TECHNICAL BRIEF
3.3.2 Block Description
The OMAPV1030 E-GPRS multimedia device is based on an OMAP3.4 platform that integrates:
_ The MPU subsystem
_ The DSP subsystem
_ A system DMA
_ A traffic controller providing:
_ External memory interfaces with:
_ A slow interface (EMIFS) to ROM, SRAM, FLASH memories
_ A fast interface (EMIFF) to SDRAM memories
_ Layer 3 (L3) interconnect made of two OCP target ports (OCP-T1 and OCP-T2) and one OCP initiator port (OCP-I)
_ Layer 4 (L4) interconnect made of two DSP peripheral busses (private DSP TIPB and shared DSP TIPB) and two
MPU peripheral busses (public MPU TIPB and private MPU TIPB)
_ Clock management
_ A set of processor peripherals:
_ Three 32-bit timers, a 16-bit Watchdog timer, and an interrupt handler for the MPU
_ Three 32-bit timers, a 16-bit Watchdog timer, and a 2nd-level interrupt handler for the DSP
_ Test and debug interfaces (JTAG, Window Tracer)
_ Trace capabilities: ETM9 and Ctools
The other OMAPV1030 modules or subsystems are connected to the OMAP3.4 platform through the L3 and L4
interconnects.
<Fig.7> OMAPV1030 Top-Level Architecture Overview
The OMAP3.4 platform is the computing core of the device. The other OMAPV1030 components are organized as
follows:
_ The internal memory subsystem is made of a single-port 256K-bit shared internal SRAM.
_ The security subsystem is a set of several components, including dedicated a secure mode to run secure
applications.
_ A master-slave USB module provides an external interface supporting high data transfer rates between the
OMAPV1030 and external application
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