LG GT500 - Page 31

- 32 -
LGE Internal Use Only Copyright © 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
3. TECHNICAL DESCRIPTION
G. GT500 Bluetooth Schematic
Figure 3-1-11. Schematic of STLC2593C
y Clock
- Clock request
Æ Connected to CLKREQ of DB3200 and AB3100, input to RF3300
-Fast clock : 26MHz
Æ Supplied MCLK from RF3300
Æ Frequency deviation : 20ppm
- Low power clock : 32.768kHz
Æ Supplied RTCCLK from AB3100
y Power
- Supplied 2.75V, 1.8V from internal regulators of AB3100
y Reset
- RESOUT2n signal of DB3200 controls STLC2593C reset.
y SPI
- Connected to SPI of DB3200
- HCI interface between DB3200 and STLC2593C
y PCM
- Audio signal interface between DB3200/AB3100 and STLC2593C
y ANT
- 2.4GHz, 50 ohm matching
Keep away from noise signals
on L1, L2 and L3
Common GND on L1, L2 and L3
Careful routing of BT_CLK
Analog GND must be Isolated from
RF GND: Isolate from Common GND
VDD_BT
R734 100K
C734
0.1u
120p C743
DEA212450BT-7043C1
5
BP1
4
BP2 BP_DC
2
3
G1
6
G2
1
U_BP
VDDE_1V8
FL730
VBAT
R739
110
0
R735
110
R741
VDDK_2V75
VSS_BT_ANA
10pC742
100K R732
A
2
3
GND
5
VCC
Y
4
1
_OE
SN74LVC1G125DRLRU730
VDD_BT
C739
0.1u
VDDK_2V75
FB730
60
VDDE_1V8
100K R738
DNIR733
C735 0.1u
C730
0.1u
C736 0.1u
R740
0
22nC741
VDDE_1V8
VDDE_1V8
VDDE_1V8
VDDE_1V8
4.7u
C731
R730
33
R737
0
1uC737
VSS_BT_ANA
VDDE_1V8
100pC732
VSS_BT_RF
VSS_BT_RF
1uC738
R731 100K
C740 22n
VDDE_1V8
C733
0.1u
L5
L6
NC6
A5
FM_LOUT
B5
FM_RCLK
D7
C8
FM_RFGND
C5
FM_ROUT
C9
FM_RSTB
E9
FM_SCLK
FM_SDIO
D8
FM_SENB
D9
FM_VA
A4
FM_VD
B3
FM_VIO
D6
D4
NC1
NC2
F7
F8
NC3
NC4
L4
NC5
H1
L1
BT_VSSRF2
BT_VSSRF3
J2
K2
BT_VSSRF4
BT_WAKEUP
L9
B8
FM_FMIP
FM_GND1
A3
B4
FM_GND2
FM_GND3
B6
FM_GND4
B7
C4
FM_GND5
C6
FM_GND6
C7
FM_GND7
FM_GND8
D5
FM_GPIO1
A7
A6
FM_GPIO2
FM_GPIO3
G4
H3
BT_VSSANA11
H4
BT_VSSANA12
D2
BT_VSSANA2
BT_VSSANA3
E3
BT_VSSANA4
F1
F2
BT_VSSANA5
BT_VSSANA6
F3
F4
BT_VSSANA7
G1
BT_VSSANA8
G3
BT_VSSANA9
H6
BT_VSSDIG1
H7
BT_VSSDIG2
BT_VSSDIG3
H8
K8
BT_VSSDIG4
L8
BT_VSSDIG5
BT_VSSRF1
C1
C2
BT_RSVR_N
BT_RSVR_RF
M2
BT_TEST1
H2
G2
BT_TEST2
BT_UART_CTS
K6
J6
BT_UART_RTS
BT_UART_RXD
H9
G7
BT_UART_TXD
E6
BT_VDD_CLD
M6
BT_VIO_A
BT_VIO_B
J9
BT_VIO_C
N3
N5
BT_VIO_D
BT_VIO_E
G8
BT_VSSANA1
D1
BT_VSSANA10
E2
E4
BT_HVA5
BT_HVD
N7
BT_LP_CLK
K9
BT_PCM_A
K5
M5
BT_PCM_B
M4
BT_PCM_CLK
N4
BT_PCM_SYNC
BT_REF_CLK_IN
F6
BT_REG_CTRL
J4
K7
BT_RESETN
J1
BT_RFN
BT_RFP
K1
BT_RSVR_CL1
B2
BT_RSVR_CL2
C3
M8
BT_RSVR_D
BT_RSVR_DSM
BT_CLK_REQ_IN_2
J7
BT_CLK_REQ_OUT_1
J8
BT_CLK_REQ_OUT_2
BT_CONFIG_1
L7
BT_CONFIG_2
M7
N6
BT_CONFIG_3
BT_GPIO_0
G9
K4
BT_GPIO_10
K3
BT_GPIO_11
BT_GPIO_16
J3
L3
BT_GPIO_8
BT_GPIO_9
M3
BT_HOST_WAKEUP
E8
BT_HVA1
L2
D3
BT_HVA2
BT_HVA3
E1
BT_HVA4
STLC2593U731
BT_AF_PRG
G6
BT_CLK_REQ_IN_1
E7
F9
VDD_BT
0R742
RESOUT2_n
PCM_DLD
PCM_ULD
PCM_CLK
PCM_SYNC
BT_CLKREQ_n
BT_TXRX
RESOUT1_n
FM_LP
FM_RP
PTA_BT_STATE
PTA_BT_PRIO
BT_CLKREQ_n
BT_CLK
MCLKSEC
ACC_GP_SPI_BT_CSn
RTCCLK
APP_I2C_SCL
APP_I2C_SDA
BT_CLK
FM_ANT
WLAN_SLEEPn
ACC_SPI_MOSI
PTA_WLAN_ACTIVE
ACC_GP_SPI_BT_IRQ
RTCCLK
ACC_SPI_CLK
ACC_SPI_MISO
APP_GP_FM_GPIO2