LG LAEC015 - FPGA board (Arria5)

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Only training and service purposes.
2. FPGA board(Arria5)
FPGA IC
DDR3(4Gbit) X 2EA
DDR3(4Gbit) X 2EA
512 Mbit
(QSPI)
Ethernet PHY
(x 4EA)
Ethernet PHY
(x 4EA)
LAN X 4EA
LAN X 4EA
Vx1 In
Vx1 60Hz
J-TAG
(JTAG DEBUG 8P)
TCK/TDI/TMS/TDO
LAN_RESET
M16++
I2C
BANK 7A
FPGA_RESET
QSPI Update
Wafer
(27Mhz)
(50 Mhz)
4EA
(25Mhz)
BANK 4A
BANK 8D
4EA
(25Mhz)
MDIO0
MDC0
#0/3_GTXCLK
#0/3_TXD0~3
#0/3_PHY_INT
#0/3_TXEN
BANK 3A
FPPDATA1/2/3/4
TCK/TDI/TMS/TDO
#0/3_MDI0/4_P/N
#0/3_LED_LINK/ACT
BANK 7B
#0/3_RXCLK
#0/3_RXD0/3
+3.3V_NORMAL
#0/3_ETH_PHYRSTB
Control Jack I2C / GPIO
HTPDN_o
LOCKn_OUT
+3.3V_NORMAL FPGA_rst_n_#1
ST
(In)
Vx1 Clock Out
Vx1 Rx
+3.3V_NORMAL
Rx_rst_n(Vx1)
+3.3V_NORMAL
Tx_rst_n(Vx1)
Vx1 Tx