LG LB45 Series - Block Diagram

- 18 -
LGE Internal Use OnlyCopyright © LG Electronics. Inc. All rights reserved.
Only for training and service purposes
MSTAR M1A
COMPONENT
RGB
HDMI1
DSUB R/G/B/H/V
Audio IN
HP L & R out
COMP_Y , Pb ,Pr
COMP_L & R_IN
USB (Jpeg,MP3,DVIX)
LGIT Half NIM (TDJH-H101F)
IF_AGC_MAIN
IF_P IF_N
DDR3 SDRAM
(1G)
NAND Flash
TU_SDA&SCL
SERIAL Flash
F_RB PF-OE PF_CEO
SPI_CK SPI_CI SPI_CS SPI_DO
DDR3 Data[0:15]
DDR3 Address[0:12]
System EEPROM
EEPROM SCL & SDA
Panel
Digital amp (TAS5733)
SP (L)
SP (R)
Audio_ Master_CLK /DATA[3] ,
12.07Mhz
HP L/R
H/P
AMP SCL&SDA
CVBS
XTAL : 24MHz
TMDS : 148.5MHz
HDMI2 & MHL
HDMI_TMDS & HDMI I2C
HDMI_TMDS & HDMI I2C
--NTSC/ATSC: TDJH-H101F(Half NIM)
*Tuner country Option
H
D
M
I
2
&
M
H
L
*DDR3 (793Mhz)
: Only PIP
MT75, MT55 Use MT45,Not use
H
/
P
*HDMI Option MT75, MT55 2EA Use MT45, MT45A 1EA use
MT55/75 : LVDS 2ch, 1920x1080,60hz , 175Mhz(Max)
MT45 : LVDS 1ch, 1366x768,60hz, 82Mhz (Max)
BLOCK DIAGRAM