VREF_DAC_MPP_3
+1V225_VREG_LPDDR
VREF_LPDDR3_CA
16 15 14 13 12 11 10 9
8
7 6 5 4 3 2 1
L
K
J
I
H
G
F
E
D
C
B
A
L
K
J
I
H
G
F
E
D
C
B
A
16 15 14 13 12 11 10 9
8
7 6 5 4 3 2 1
DRAWN BY
SIZE
DWG NO
REV
TITLE
SHEET
of
A2
LG Electronics
Date
LGE Internal Use Only
Drawing Date
+1V8_VREG_S4A
GND
WTR0_DRXBB_Q_CA1
WTR0_PRXBB_I_CA1
WTR0_PRXBB_Q_CA1
WTR0_GNSSBB_Q
WTR0_GNSSBB_I
WTR0_PRXBB_I_CA2
WTR0_PRXBB_Q_CA2
WTR0_DRXBB_I_CA2
WTR0_DRXBB_Q_CA2
WTR0_DRXBB_I_CA1
WTR0_TX_FB_I
WTR0_TX_FB_Q
MAIN_CAM0_MIPI_DATA1_P
MAIN_CAM0_MIPI_DATA1_N
MAIN_CAM0_MIPI_DATA0_P
MAIN_CAM0_MIPI_DATA0_N
MAIN_CAM0_MIPI_CLK_P
MAIN_CAM0_MIPI_CLK_N
MAIN_CAM0_MIPI_DATA2_P
MAIN_CAM0_MIPI_DATA2_N
MAIN_CAM0_MIPI_DATA3_N
VT_CAM_MIPI_CLK_P
VT_CAM_MIPI_CLK_N
PMIC_SPMI_DATA
VT_CAM_MIPI_DATA0_N
VT_CAM_MIPI_DATA0_P
MAIN_CAM0_MIPI_DATA3_P
PMIC_SPMI_CLK
WLAN_CLK
eMMC_CLK
LCD_MIPI0_DATA3_N
LCD_MIPI0_DATA3_P
LCD_MIPI0_CLK_N
LCD_MIPI0_CLK_P
LCD_MIPI1_DATA2_N
LCD_MIPI1_DATA2_P
LCD_MIPI1_DATA1_N
LCD_MIPI1_DATA1_P
LCD_MIPI1_DATA0_P
LCD_MIPI1_DATA0_N
LCD_MIPI1_CLK_N
LCD_MIPI1_CLK_P
LCD_MIPI1_DATA3_N
LCD_MIPI1_DATA3_P
LCD_MIPI0_DATA0_N
LCD_MIPI0_DATA0_P
LCD_MIPI0_DATA1_N
LCD_MIPI0_DATA1_P
LCD_MIPI0_DATA2_N
LCD_MIPI0_DATA2_P
MSM_USB_HS1_D_P
MSM_USB_HS1_D_M
HDMI_TMDS_TCLK_P
HDMI_TMDS_TCLK_N
HDMI_TMDS_TX0_N
HDMI_TMDS_TX0_P
HDMI_TMDS_TX2_P
HDMI_TMDS_TX2_N
HDMI_TMDS_TX1_N
HDMI_TMDS_TX1_P
JTAG_TDI
JTAG_TDI
JTAG_TDO
JTAG_TDO
JTAG_TMS
JTAG_TMS
JTAG_TCK
JTAG_TCK
BBCLK1_CXO
LNBBCLK_CXO2
JTAG_RESOUT_N
JTAG_RESOUT_N
JTAG_TRST
JTAG_TRST
VT_CAM_MIPI_DATA1_P
VT_CAM_MIPI_DATA1_N
VT_CAM_MIPI_DATA2_N
VT_CAM_MIPI_DATA2_P
VT_CAM_MIPI_DATA3_N
VT_CAM_MIPI_DATA3_P
eMMC_DATA_0
eMMC_DATA_1
eMMC_DATA_2
eMMC_DATA_3
eMMC_DATA_4
eMMC_DATA_5
eMMC_DATA_6
eMMC_DATA_7
eMMC_CMD
MSM_RESOUT_N
SLEEP_CLK
BBCLK1_EN
JTAG_PS_HOLD
MSM_PS_HOLD
MSM_RESIN_N
WLAN_SDIO_1
WLAN_SDIO_3
WLAN_SDIO_2
WLAN_SDIO_0
WLAN_CMD
eMMC_DS
SDCARD_DATA_0
SDCARD_DATA_1
SDCARD_CMD
SDCARD_CLK
SDCARD_DATA_3
SDCARD_DATA_2
11/22
VZW Change
< 2-1-9-1-1 MSM8992 CONTROL > Rev.0.1
QCT Schematic Review (4/9)
- Ground all TX_DAC1 signals
if they are not used
if they are not used
Used to mitigate possible HW issue.
run simulation to make sure reflections do not violate threshold levels.
Add DNI caps to SPMI_DATA and SPMI_CLK
QCT Schematic Review (4/9)
- Ground all ET_DAC0/1 signals
eMMC
- Minimum total bus capacitance of 15 pF should be met
Based on Reference Schematic
Release Date
CCDS CARD Information
- VDD_UFS_1P8 and VDD_UFS_CORE must be powered.
- Leave all SDC2 signals floating if SD CARD is not used.
- Leave all SDC1 signals floating if eMMC is not implemented.
USB 3.0
- Leave USB1_SS_RX/TX pin floating if USB3.0 is not implemented.
USB2_HS
- Connect USB2_HS_DP/DM to GND if USB2_HS is not used.
REXT resistors
close to MSM.
SD CARD
if eMMC v4.5 or lower is implemented.
- Leave SDC1_RCLK floating & change R2113 value to 33 ohm.
- Place R2114 on clk line close to MSM.
- Place R2113 on clk line close to MSM.
- Place all REXT resistors
if eMMC v5.0 use, SDC1_RCLK need to rout to eMMC
01/20 R2146 should be closed to MSM
< JTAG >
- We will use USB2_HS for AppsPort
7/23
WTR0_TXBB_I_P
WTR0_TXBB_I_N
WTR0_TXBB_Q_P
WTR0_TXBB_Q_N
15/03/02
Rev.10 Change
R2118
200K
DNI
C2111
200R2107 TOL=0.01
TOL=0.01240R2101
C2106 0.1u
R2113 24 TOL=0.01
C2109
DNI
TP2102
TP2101
R2109 TOL=0.011.43K
R2104 TOL=0.01240
1.43KTOL=0.01R2110
TOL=0.011.43KR2111
R21121.43KTOL=0.01
33nC2101
33nC2100
33nC2102
240 TOL=0.01R2103
240 TOL=0.01R2102
TOL=0.0133R2114
C2103 33n
TOL=0.0133R2115
L1704
22n
L1706
22n
L1705
22n
L1707
22n
C2112
3.3p
C2113
3.3p
C2114
3.3p
C2115
3.3p
G1 G2
G3 G4
1 10
2 9
3 8
4 7
5 6
CN2200
C2110
DNI
U2100
BF27
BJ36
BG36
BG34
BH35
BH31
BJ32
BJ30
BG30
BH33
BJ34
BE20
BJ28
BG28
BG26
BJ26
BH23
BG24
BG22
BJ22
BJ24
BH25
B19
D19
A18
C18
B17
D17
C14
D15
B15
C16
D25
B25
C24
A24
D23
B23
C20
D21
B21
C22
D31
C32
C30
B31
B29
D29
B27
D27
A28
C28
BH15
BH19
BG20
BG18
BJ18
BJ16
BH17
BJ20
BH21
AR50
AP49
AT49
AR48
AN50
AN48
AP47
BH29
BF13
BE32
BD37
AN2
AL50
H21
G36
G14
A34
BF49
BK29
BK37
BD29
J4
H7
D3
J6
G10
H5
BD3
BF5
BE12
BE4
BE2
BC4
BH3
AM43
B9
BB3
BC2
AM49
BH43
BG44
AL48
BH47
BG48
BF47
BE46
BB49
BF45
BH45
BG46
T7
T5
V5
V7
U6
W6
K3
J2
L4
M3
N4
L2
B33
C34
D39
D37
D33
B35
C40
C38
B39
C36
D35
U44
U46
V47
V45
AC42
AD47
AD49
AG42
AH47
AH45
AE42
AB45
AB47
AC48
AC46
AF43
AF49
AF47
AG46
AG48
E46
E48
F47
F45
G46
G48
H47
H45
K47
K45
J44
J46
M47
M45
L44
L46
N44
N46
P47
P45
W44
W46
Y47
Y45
R44
R46
T47
T45
BBRX_IP_CH0
BBRX_IM_CH0
BBRX_QP_CH0
BBRX_QM_CH0
BBRX_IP_FB/BBRX_IP_CH4
BBRX_IM_FB/BBRX_IM_CH4
BBRX_QP_FB/BBRX_QP_CH4
BBRX_QM_FB/BBRX_QM_CH4
BBRX_IP_CH1
BBRX_IM_CH1
BBRX_QP_CH1
BBRX_QM_CH1
BBRX_IP_CH2
BBRX_IM_CH2
BBRX_QP_CH2
BBRX_QM_CH2
BBRX_IP_CH3
BBRX_IM_CH3
BBRX_QP_CH3
BBRX_QM_CH3
BBRX_IP_CH5
BBRX_IM_CH5
BBRX_QP_CH5
BBRX_QM_CH5
BBRX_IP_CH6
BBRX_IM_CH6
BBRX_QP_CH6
BBRX_QM_CH6
TX_DAC0_IP
TX_DAC0_IM
TX_DAC0_QP
TX_DAC0_QM
TX_DAC0_VREF
TX_DAC1_IP
TX_DAC1_IM
TX_DAC1_QP
TX_DAC1_QM
TX_DAC1_VREF
ET_DAC0_P
ET_DAC0_M
ET_DAC0_VREF
ET_DAC1_P
ET_DAC1_M
ET_DAC1_VREF
GNSS_BB_IP
GNSS_BB_IM
GNSS_BB_QP
GNSS_BB_QM
SDC1_RCLK
SDC1_CLK
SDC1_CMD
SDC1_DATA_0
SDC1_DATA_1
SDC1_DATA_2
SDC1_DATA_3
SDC1_DATA_4
SDC1_DATA_5
SDC1_DATA_6
SDC1_DATA_7
SDC2_CLK/QDSS_SDC2_TRCLK
SDC2_CMD/QDSS_SDC2_TRSYNC
SDC2_DATA_0/QDSS_SDC2_TRDATA_0
SDC2_DATA_1/QDSS_SDC2_TRDATA_1
SDC2_DATA_2/QDSS_SDC2_TRDATA_2
SDC2_DATA_3/QDSS_SDC2_TRDATA_3
SDC3_CLK
SDC3_CMD
SDC3_DATA_0
SDC3_DATA_1
SDC3_DATA_2
SDC3_DATA_3
USB1_HS_DP
USB1_HS_DM
USB1_HS_ID
USB1_HS_REXT
USB1_SS_RX_P
USB1_SS_RX_M
USB1_SS_TX_P
USB1_SS_TX_M
USB1_SS_REXT
USB2_HS_DP
USB2_HS_DM
USB2_HS_REXT
PMIC_SPMI_CLK
PMIC_SPMI_DATA
CXO
CXO_2
CXO_EN
SLEEP_CLK
RESIN_N
RESOUT_N
MODE_0
MODE_1
PS_HOLD
SRST_N
TCK
TDI
TDO
TMS
TRST_N
EBI0_CAL
EBI1_CAL
EBI_ZQ_A
EBI_ZQ_B
VREF_EBI_01
VREF_EBI_02
VREF_EBI_03
VREF_EBI_04
VREF_EBI_05
VREF_EBI_06
VREF_EBI_07
VREF_EBI_08
VREF_EBI_09
VREF_EBI_10
PCIE0_REF_CLK_P
PCIE0_REF_CLK_M
PCIE0_REXT
PCIE0_RX_P
PCIE0_RX_M
PCIE0_TX_P
PCIE0_TX_M
HDMI_TCLK_P
HDMI_TCLK_M
HDMI_TX0_P
HDMI_TX0_M
HDMI_TX1_P
HDMI_TX1_M
HDMI_TX2_P
HDMI_TX2_M
HDMI_REXT
MIPI_CSI0_CLK_P
MIPI_CSI0_CLK_N
MIPI_CSI0_LN0_P
MIPI_CSI0_LN0_N
MIPI_CSI0_LN1_P
MIPI_CSI0_LN1_N
MIPI_CSI0_LN2_P
MIPI_CSI0_LN2_N
MIPI_CSI0_LN3_P
MIPI_CSI0_LN3_N
MIPI_CSI1_CLK_P
MIPI_CSI1_CLK_N
MIPI_CSI1_LN0_P
MIPI_CSI1_LN0_N
MIPI_CSI1_LN1_P
MIPI_CSI1_LN1_N
MIPI_CSI1_LN2_P
MIPI_CSI1_LN2_N
MIPI_CSI1_LN3_P
MIPI_CSI1_LN3_N
MIPI_CSI2_CLK_P
MIPI_CSI2_CLK_N
MIPI_CSI2_LN0_P
MIPI_CSI2_LN0_N
MIPI_CSI2_LN1_P
MIPI_CSI2_LN1_N
MIPI_CSI2_LN2_P
MIPI_CSI2_LN2_N
MIPI_CSI2_LN3_P
MIPI_CSI2_LN3_N
MIPI_DSI0_CLK_P
MIPI_DSI0_CLK_N
MIPI_DSI0_LN0_P
MIPI_DSI0_LN0_N
MIPI_DSI0_LN1_P
MIPI_DSI0_LN1_N
MIPI_DSI0_LN2_P
MIPI_DSI0_LN2_N
MIPI_DSI0_LN3_P
MIPI_DSI0_LN3_N
MIPI_DSI0_REXT
MIPI_DSI1_CLK_P
MIPI_DSI1_CLK_N
MIPI_DSI1_LN0_P
MIPI_DSI1_LN0_N
MIPI_DSI1_LN1_P
MIPI_DSI1_LN1_N
MIPI_DSI1_LN2_P
MIPI_DSI1_LN2_N
MIPI_DSI1_LN3_P
MIPI_DSI1_LN3_N
MIPI_DSI1_REXT
MSM8992-B
H815
2-1 MSM8992_Control
25
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