2-25
Pin No. Port Name I/O FUNCTION
127-130
133-139 CPUADT0-15 I/O CPU address/data bus.
143-147
141 XRESET I Global reset input.
148-152 CPUADT16-20 I CPU address bus.
153 XALE I Address latch enable input.
154 XRE I Read strobe.
155 XINTO O ECC interrupt request.
158 XWEH I Write strobe signal.
159 XWAIT O CPU wait state control.
168 XHSTCS O Decipher chip select.
176 STENABLE I Stream data request.
177-181
STD0-7 O Output stream data bus.
185-187
183 GENCLK I 27 MHz clock input.
188 STCLK O Output stream data transfer clock, falling edge active, 6.75 MHz.
189 STVALID O Output stream data valid.
190 XVCS O Latched video decoder chip select.
191 XVDS O CPU read/write strobe.
192 HRXW O CPU write strobe, XWEH
193 ASCK O Latched audio decoder chip select.
207 SELCPU I 1: data corresponds to CPUADT15-8. 0: data corresponds to CPUADT7-0.
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