Marvell ARMADA 88F6810 - User Manual

Marvell. Moving Forward Faster
Doc. No. MV-S302310-U0, Rev. A
August 30, 2017
Document Classification: Public
88F6810, 88F6820 and 88F6828 Hardware Design Guide
88F6810, 88F6820 and
88F6828
ARMADA
®
38x Family
High-Performance Single/Dual Core
CPU System on Chip
Hardware Design Guide

Summary

Introduction and Relevant Devices

Relevant Devices

Identifies the specific Marvell devices for which this document is relevant.

Related Documents

Lists other documents containing additional information for the specified devices.

4-Layer Board Recommendations

Stack-Up Example

Provides a 4-layer PCB stack-up example for impedance matching.

General Guidelines

Offers general trace routing and board design guidelines for 5 mil traces.

Power Filtering

Discusses power filtering requirements for analog power pins.

Generic Guidelines for SERDES Interfaces

Insertion Loss and Loss Budget

Explains insertion loss and loss budget concepts for high-speed serial interfaces.

Inter-Symbol Interference (ISI)

Defines Inter-Symbol Interference and its impact on eye patterns.

PCB Materials Selection

Details parameters for selecting PCB materials for high-speed interfaces.

Crosstalk

Discusses crosstalk phenomena and its impact on signal integrity.

Return Path Continuity

Emphasizes the importance of a continuous return current path for signal quality.

Target Routing Impedance

Provides guidelines for achieving target differential and single-ended impedances.

Capacitive Discontinuities

Addresses capacitive discontinuities and their effect on insertion loss.

Via Structures

Details via structures and their impact on signal integrity.

Generic Power Board Guidelines

Generic Power Network Guidelines

Covers power network design, loop inductance, and decoupling capacitors.

Analog Power Filtering

Provides guidelines for analog power filtering and decoupling capacitors.

Core Power Decoupling

Addresses core power decoupling requirements and implementation notes.

I;O Power Bypassing

Details I/O power bypassing, focusing on return path continuity.

Bulk Capacitors

Recommends bulk capacitance for power polygons and resonance suppression.

Termination Voltage (VTT) Layout Recommendations

Provides layout recommendations for VTT termination voltage.

Unused Interface

JTAG Connection Information

16-bit SDRAM DDR3 Interface

Interface Connectivity

Describes DDR3 SDRAM interface signals and their connection to devices.

Interface Signals Layout Guidelines

Provides layout guidelines for 16-bit SDRAM DDR3 signals.

Special Software Setting

Details ODT control matrix and driver configuration for DDR3.

32-bit SDRAM DDR3 Interface

Interface Connectivity

Describes DDR3 SDRAM interface signals and their connection to devices.

Interface Signals Layout Guidelines

Provides layout guidelines for 32-bit SDRAM DDR3 signals.

32-bit SDRAM DDR4 Interface

Interface Connectivity

Describes DDR4 SDRAM interface signals and their connection to devices.

Interface Signals Layout Guidelines

Provides layout guidelines for 32-bit SDRAM DDR4 signals.

Network Ethernet Ports

Reduced Gigabit Media Independent Interface (RGMII)

Interface Connectivity

Details RGMII interface signal groups and connectivity.

Interface Signals Layout Guidelines

Provides routing constraints and topologies for RGMII interface.

Serial Gigabit Media Independent Interface (SGMII)

Interface Connectivity

Details SGMII interface signal groups and connectivity.

Interface Signals Layout Guidelines for Chip-to-Chip End-to-End Connection

Provides routing constraints for SGMII chip-to-chip connections.

High Speed Serial Gigabit Media Independent Interface (HS-SGMII)

Interface Connectivity

Details HS-SGMII interface signal groups and connectivity.

Interface Signals Layout Guidelines

Provides routing constraints for HS-SGMII interfaces.

Quad Serial Gigabit Media Independent Interface (QSGMII)

Interface Connectivity

Details QSGMII interface signal groups and connectivity.

Interface Signals Layout Guidelines for Chip-to-Chip End-to-End Connection

Provides routing constraints for QSGMII chip-to-chip connections.

PCI Express (PCIe) Interface 1.0;1.1

Connectivity

Describes PCIe 1.0/1.1 interface signal groups and connectivity.

Interface Signals Layout Guidelines

Provides layout guidelines for PCIe 1.0/1.1 signals.

PCI Express (PCIe) Interface 2.0

Connectivity

Describes PCIe 2.0 interface signal groups and connectivity.

Interface Signals Layout Guidelines

Provides layout guidelines for PCIe 2.0 signals.

Universal Serial Bus (USB) 2.0 Interface

Interface Connectivity

Details USB 2.0 interface pin connectivity groups.

Interface Signals Layout Guidelines

Provides USB 2.0 routing constraints and topologies.

Universal Serial Bus (USB) 3.0 Interface

General Design Considerations

Discusses design considerations for USB 3.0 host or device.

Interface Connectivity

Details USB 3.0 interface pin connectivity groups.

Serial ATA (SATA) Interface 3.0

Connectivity

Describes SATA 3.0 interface signal groups and connectivity.

Interface Signals Layout Guidelines

Provides SATA 3.0 layout guidelines and connection topologies.

SDIO 3.0 and MMC 4.4

Interface Connectivity

Details SDIO 3.0/MMC 4.4 interface signal groups.

Connectivity

Shows SDIO 3.0/MMC 4.4 port connection to a connector.

Serial Management Interface (SMI)

Interface Connectivity

Describes SMI interface connectivity and modes.

Interface Signals Layout Guidelines

Provides general tips and guidelines for SMI signal layout.

Device Bus Interface

Device Bus Interface Connectivity

Provides guidelines for connecting and using the device bus interface.

NAND Flash Support

Details NAND Flash connectivity via the Device bus.

General Clock Guidelines

Core Clock

Provides connectivity and constraints for the core clock.

Single-ended Clock Distribution

Recommends connectivity for single-ended clock distribution.

ARMADA 38 x Family Clock Topology

Clock Topology

Presents all required clocks for the device.

PCI Express Clock Topology

Details PCI Express interface clock topology options.

Adaptive Voltage Scaling (AVS)

Connectivity

Explains AVS connectivity to power regulators and feedback inputs.

Marvell ARMADA 88F6810 Specifications

General

Architecture	ARMv7
CPU	ARM Cortex-A9
Instruction Set	ARMv7
Process Technology	40 nm
L2 Cache	512 KB
Integrated GPU	No
Memory Speed	Up to 1066 MHz
USB Support	USB 2.0
SATA	SATA 3.0
TDP	5 W
PCI Express	PCIe 2.0
L1 Cache	32 KB
Memory Support	DDR3
Ethernet	1 Gbps
Security Features	TrustZone