Name: Marvell ARMADA 88F6810
Brand: Marvell
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Doc. No. MV-S302310-U0, Rev. A

August 30, 2017

Document Classification: Public

88F6810, 88F6820 and 88F6828 Hardware Design Guide

88F6810, 88F6820 and

88F6828

ARMADA

38x Family

High-Performance Single/Dual Core

CPU System on Chip

Hardware Design Guide

Table of Contents4
Revision History13
Introduction13
Table 1: Revision History13
Table 1: Related Documents14
4-Layer Board Recommendations15
Stack-Up Example15
Table 2: 4-Layer Stack up Example15
General Guidelines16
88F6810, 88F6820 and 88F6828 Power Filtering17
Routing Guidelines for the ISET Signal18
Board Recommendations for Stripline Routing PCB18
Table 3: List of Capacitors18
Generic Guidelines for SERDES Interfaces19
Insertion Loss and Loss Budget19
Figure 1: Insertion Loss Curve20
Inter-Symbol Interference (ISI)22
Figure 2: Typical Trace Differential Amplitude Insertion Loss and ISI22
Figure 3: Difference in Attenuation Due to ISI - Time Domain Influence23
Figure 4: ISI Originated Jitter - Eye Pattern23
Placement of Devices and Connectors on the Board24
PCB Materials Selection25
Crosstalk26
Figure 5: Stack-Up Cross-Section with a High Probability of Crosstalk27
Return Path Continuity28
Figure 6: Non-Continuous Reference Plane Return Current Path Influence29
Figure 7: Layer Transfer29
Target Routing Impedance30
Figure 8: Reference Plane Clearance31
Figure 9: Changed Width for Differential Impedance Compensation32
Capacitive Discontinuities33
Figure 10: Voids Underneath AC Coupling Capacitors' Pads33
Figure 11: Voids Underneath BGA Device Ball34
Figure 12: Voids Underneath SMT Connector/Qfp Lead Frame Pads34
Trace Symmetry and Matching-Mode Conversion35
Via Structures35
Figure 13: Proper Deskew35
Figure 14: Via Structures36
Figure 15: Via Stubs37
Figure 16: Differential Via Structure37
Figure 17: Recommended Via Structure Dimensions for SERDES Interface up to 12.5 Gbps38
Selecting the Appropriate Components39
Figure 18: Recommended Via Structure Dimensions for 25 Gbps SERDES Interfaces39
Generic Power Board Guidelines40
Generic Power Network Guidelines40
DC Voltage Drop41
Polygon Shape Considerations41
Figure 19: Coupling of Vias41
Figure 20: Routing Length between the Capacitor and the Vias41
Analog Power Filtering42
Figure 21: Required Analog Power Filter Voltage Transfer Function42
Figure 22: Analog Power Filter Example43
Table 4: Definition of Analog Power Filter Symbols43
Core Power Decoupling44
I/O Power Bypassing44
Bulk Capacitors45
Figure 23: Return Path Discontinuity-Bypass Capacitor45
Figure 24: Placement of a Bypass Capacitor in Relation to Device Ground Pins45
Termination Voltage (VTT) Layout Recommendations46
Unused Interface47
JTAG Connection Information48
Figure 25: JTAG Connection48
16-Bit SDRAM DDR3 Interface49
Interface Connectivity49
Table 5: Signal Groups50
Figure 26: on Board 1X16-Bit Wide Memory Device with ECC Connected to the Controller51
Figure 27: on Board 2X8-Bit Wide Memory Devices with ECC Connected to the Controller52
Figure 28: on Board 16-Bit, 4X8-Bit Wide Memory Devices with ECC Connected to the Controller53
Interface Signals Layout Guidelines54
Figure 29: on Board 16-Bit, 1X16-Bit Wide Memory with ECC Topology-Address and Control55
Figure 30: on Board 16-Bit, 1X16-Bit Single-Side Assembly Topology with ECC-Data56
Table 6: Routing Constraints When Using on Board 16-Bit, 1X16-Bit Wide Memory Topology57
Figure 31: on Board 16-Bit, 2X8-Bit Wide Memory Topology with ECC -Address58
Figure 32: On-Board 16-Bit, 2X8-Bit with ECC, Single-Side Assembly Topology-Data59
Table 7: Routing Constraints-On-Board 16-Bit, 2X8-Bit Topology60
Figure 33: on Board 16-Bit, 4X8-Bit Wide Memory Topology for Clock/Address/Command/Control with62
Figure 34: on Board 16-Bit, 4X8-Bit Wide Memory with ECC Topology for Data63
Table 8: Routing Constraints When Using on Board 16-Bit, 4X8-Bit Wide Memory Topology Using a64
Special Software Setting65
Table 9: ODT Control Matrix for SDRAM DDR3 with 1 Chip Select65
Table 10: ODT Control Matrix for SDRAM DDR3 with 2 Chip Selects Using a Clamshell Assembly65
32-Bit SDRAM DDR3 Interface66
Interface Connectivity66
Table 11: Signal Groups66
Figure 35: On-Board 32-Bit 2 Memory Devices, 2X16-Bit Single-Side Connectivity68
Figure 36: On-Board 32-Bit, 4X8-Bit Single-Side Connectivity69
Figure 37: On-Board 32-Bit, 8X8-Bit Clamshell Connectivity with ECC70
Interface Signals Layout Guidelines71
Figure 38: On-Board 32-Bit, 2X16-Bit Single-Side Assembly Topology-Address and Control with ECC72
Figure 39: On-Board 32-Bit, 2X16-Bit Single-Side Assembly Topology with ECC-Data73
Table 12: Routing Constraints-32-Bit, 2X16-Bit Single Side Assembly Topology73
Figure 40: On-Board 32-Bit, 4X8-Bit Single-Side Assembly Topology with ECC-Address and Control76
Figure 41: On-Board 32-Bit, 4X8-Bit, with ECC, Single-Side Assembly Topology-Data77
Table 13: Routing Constraints-On-Board 32-Bit with or Without ECC, 4X8-Bit Topology78
Figure 42: On-Board 32-Bit, 8X8-Bit Clamshell Topology with ECC-Address and Control80
Figure 43: On-Board 32-Bit, 8X8-Bit Clamshell Topology with ECC-Data81
Table 14: Routing Constraints-On-Board 32-Bit with or Without ECC, 8X8-Bit Clamshell Topology81
Power Signals83
Special Software Setting83
Table 15: ODT Control Matrix for SDRAM DDR3 with 1 Chip Select83
Table 16: ODT Control Matrix for SDRAM DDR3 with 2 Chip Selects Using a Clamshell Assembly84
32-Bit SDRAM DDR4 Interface85
Interface Connectivity85
Figure 44: On-Board 32-Bit, 4X8-Bit Single-Side Connectivity87
Interface Signals Layout Guidelines88
Figure 45: On-Board 32-Bit, 4X8-Bit Single-Side Assembly Topology with ECC-Address and Control90
Figure 46: On-Board 32-Bit, 4X8-Bit, with ECC, Single-Side Assembly Topology-Data91
Table 18: Routing Constraints-On-Board 32-Bit with or Without ECC, 4X8-Bit Topology92
Power Signals93
Special Software Setting94
Table 19: ODT Control Matrix for SDRAM DDR4 with 1 Chip Select94
Network Ethernet Ports95
Reduced Gigabit Media Independent Interface (RGMII)96
Interface Connectivity96
Connectivity96
Interface Signals Layout Guidelines97
Figure 47: RGMII Port Connection to PHY97
Figure 48: RGMII Port Connection to Another RGMII MAC97
Figure 49: RGMII Routing Topology98
Table 21: no Internal Delay on Transmitting or on Receiving Peer Side-Tx Path98
Table 22: Internal Delay on Transmitting or on Receiving Peer Side-Tx Path99
Table 23: no Internal Delay on Receiving or on Transmitting Peer Side-Rx Path100
Table 24: Internal Delay on Receiving or on Transmitting Peer Side-Rx Path100
Serial Gigabit Media Independent Interface (SGMII)101
Interface Connectivity101
Figure 50: SGMII Generic Point-To-Point Connection101
Table 17: Signal Groups101
Interface Signals Layout Guidelines for Chip-To-Chip End-To-End Connection102
Figure 51: SGMII Topology for Chip-To-Chip, End-To-End Connection102
Table 26: Routing Constraints Chip-To-Chip, End-To-End Connection102
Power Considerations104
Specific Signals104
High Speed Serial Gigabit Media Independent Interface (HS-SGMII)105
Interface Connectivity105
Figure 52: SGMII Generic Point-To-Point Connection105
Table 20: Signal Groups105
Interface Signals Layout Guidelines106
Figure 53: Topology for Chip-To-Chip, End-To-End Connection106
Table 28: Routing Constraints for a Chip-To-Chip End-To-End Connection106
Power Considerations108
Specific Signals108
Quad Serial Gigabit Media Independent Interface (QSGMII)109
Interface Connectivity109
Figure 54: QSGMII Generic Point-To-Point Connection109
Table 29: Signal Groups109
Interface Signals Layout Guidelines for Chip-To-Chip End-To-End Connection110
Figure 55: QSGMII Topology for Chip-To-Chip, End-To-End Connection110
Table 30: Routing Constraints for a Chip-To-Chip End-To-End Connection Topology110
Clock Considerations112
Power Considerations112
Specific Signals112
PCI Express (Pcie) Interface 1.0/1.1113
Connectivity113
Table 31: Signal Groups113
Table 32: Specific Device113
Figure 56: PCI Express Interface Connectivity114
Device114
Interface Signals Layout Guidelines115
Figure 58: Topology with an Existing Connector And/Or an Add-In Card115
Table 33: System Board with Existing Connector116
Table 34: Add-In Card117
Figure 59: Topology with a Same-Board Connection118
Table 35: Same-Board Connection118
Power Considerations119
Specific Signals119
PCI Express (Pcie) Interface 2.0121
Connectivity121
Table 36: Signal Groups121
Table 37: Specific Device121
Figure 60: PCI Express Interface Connectivity122
Interface Signals Layout Guidelines123
Figure 61: PCI Express Interface Connectivity and Reference Clock Supplied by Marvell ® Device123
Figure 62: Topology with an Existing Connector And/Or an Add-In Card124
Table 38: System Board with Existing Connector124
Table 39: Add-In Card126
Figure 63: Topology with a Same-Board Connection127
Table 40: Same-Board Connection127
Power Considerations129
Reference Clock Considerations129
Specific Signals129
Universal Serial Bus (USB) 2.0 Interface130
Interface Connectivity130
Figure 64: USB 2.0 Interface Connectivity to a Connector-Including Optional Common Mode Choke and Protection Diodes Circuitry130
Table 25: Signal Groups130
Table 27: Signal Groups130
Table 41: USB Interface Pin Connectivity Groups130
Figure 65: Vbus Connectivity When Configured as a Host131
Figure 66: Vbus Connectivity When Configured as a Device131
Interface Signals Layout Guidelines132
Figure 67: Topology-Including Common Mode Choke and Protection Diodes Optional Circuitry-When Configured as a Device132
Table 42: Routing Constraints When Configured as a Device132
Figure 68: Topology-Including Optional Common Mode Choke and Protection Diodes Circuitry-When Configured as a Host134
Table 43: Routing Constraints When Configured as a Host134
Power Considerations135
Specific Signals135
Universal Serial Bus (USB) 3.0 Interface136
General Design Considerations136
Interface Connectivity136
Table 44: USB Interface Pin Connectivity Groups136
Figure 69: Topology-Including Common Mode Choke and Protection Diodes Optional Circuitry-When Configured as a Device137
Table 45: Routing Constraints When Configured as a Device137
Figure 70: Topology-Including Optional Common Mode Choke and Protection Diodes Circuitry-When Configured as a Host139
Table 46: Topology-Including Optional Common Mode Choke and Protection Diodes Circuitry- When Configured as a Host139
Serial ATA (SATA) Interface 3.0141
Connectivity141
Interface Signals Layout Guidelines141
Figure 71: SATA Interface Connectivity141
Table 47: Signal Groups141
Figure 72: Topology for Connection to a Standard SATA 3.0 1-Meter Cable142
Table 48: Connection to a Standard SATA 3.0 1-Meter Cable142
Clock Considerations143
Power Considerations143
Specific Signals143
SDIO 3.0 and MMC 4.4144
Interface Connectivity144
Connectivity144
Figure 73: SDIO 3.0/MMC4.4 Connection to Connector Side144
Table 49: Signal Groups144
Figure 74: SDIO 3.0/MMC 4.4 Routing Topology145
Table 50: Routing Constraints for SDIO 3.0 and MMC 4.4 Interfaces145
Serial Management Interface (SMI)147
Interface Connectivity147
Interface Signals Layout Guidelines147
Figure 75: Clock Transition Examples148
Figure 76: Master SMI Connectivity Example148
Device Bus Interface149
Device Bus Interface Connectivity149
Figure 77: Using Two 8-Bit Flash Devices to Comprise a 16-Bit Bus149
Figure 78: Example of a 16-Bit Wide Device Connection150
Figure 79: Example of a 512 KB Flash Device with an 8-Bit Data Bus Connection151
Dev_Readyn Support152
Device Bus Interface Control Signals at Reset152
Figure 80: Dev_Readyn Connection Example152
NAND Flash Support153
Figure 81: Connectivity for Chip Enable Don't Care NAND Flash153
General Clock Guidelines154
Core Clock155
Figure 82: Core Clock Connectivity155
Table 51: Core Clock Tx/Rx Path Constraints155
Figure 83: Reference Clock Distribution156
ARMADA ® 38X Family Clock Topology157
Clock Topology157
Figure 84: Clock Topology157
PCI Express Clock Topology158
Figure 85: Internal Reference Clock with up to 2 Pcie Root Complex Ports158
Figure 86: External Reference Clock with 4 Pcie Root Complex Ports159
Figure 87: External Reference Clock with 1 Pcie Endpoint and 3 Root Complex Ports159
Figure 88: Internal Reference Clock Topology with 4 Pcie Root Complex Ports160
Figure 89: Internal Reference Clock Topology with 1 Pcie Endpoint and 3 Root Complex Ports160
Adaptive Voltage Scaling (AVS)161
Connectivity161
Figure 90: Board Connectivity for VDD_CPU with Direct AVS Feedback Connection162
Figure 91: Board Connectivity for VDD_CPU with AVS Feedback Connection with Resistor Voltage162

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Marvell ARMADA 88F6810 Specifications

General

Architecture	ARMv7
CPU	ARM Cortex-A9
Instruction Set	ARMv7
Process Technology	40 nm
L2 Cache	512 KB
Integrated GPU	No
Memory Speed	Up to 1066 MHz
USB Support	USB 2.0
SATA	SATA 3.0
TDP	5 W
PCI Express	PCIe 2.0
L1 Cache	32 KB
Memory Support	DDR3
Ethernet	1 Gbps
Security Features	TrustZone

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