Marvell GT-64260A - User Manual

GT-64260A Design Guide
Doc. No. MV-S300165-00, Rev. A
May 21, 2002

Summary

Section 2. GT-64260 A Overview

Section 3. CPU Interface Functional Overview

3.1 CPU Pinout Description

Details the pins for the GT-64260A CPU interface.

3.4 Cache Coherency

Details cache coherency support between SDRAM and CPU caches.

3.5 Specific CPUs Aspects

Covers specific PowerPC CPU considerations for GT-64260A.

3.6 Multi-GT or Multi-slave Modes

Explains connecting multiple GT-64260A devices for system flexibility.

3.7 CPU Bus Multiple Masters

Discusses arbitration for systems with multiple CPU bus masters.

Section 4. SDRAM Interface Functional Overview

4.1 Pinout Description

Details the pin assignments for the SDRAM interface.

4.2 Memory Connection

Explains how to connect various SDRAM densities and configurations.

4.4 SDRAM Initialization

Describes the sequence for initializing the SDRAM controller.

4.5 ECC Support

Explains the GT-64260A's ECC capability and considerations.

Section 5. PCI Interface Functional Overview

5.1 P2 P Capability

5.2 PCI Arbitration

5.5 Cache Coherency

Section 6. Device Interface Functional Overview

6.1 Device Connection

6.5 Signals Timing

Section 7. Communication Interface Functional Overview

7.1 Ethernet Controllers

Describes the three 10/100 Mbps Ethernet ports.

7.2 MPSC Controllers

Details the two MPSC controllers supporting UART, HDLC, etc.

7.4.1 Descriptors Management

7.5 I2 C Interface

7.5.3 Serial ROM Initialization

Section 8. Multi-Purpose Pin Interface Functional Overview

8.1 General Purpose Pin (GPP)

8.2 Interrupt Outputs

Section 9. JTAG Interface Functional Overview

Section 10. IDMA Unit Functional Overview

10.1 Chain Mode

10.2 Cache Coherency

Section 11. Interrupt Controller Functional Overview

Section 12. Messaging Units Functional Overview

12.1 Messaging

12.2 Doorbell

12.3 Circular Queue

Section 14. CPU Interface Design Considerations

14.1 CPU Interface Connectivity

14.4 Timing Requirements

Details timing calculations and requirements for the CPU interface.

14.4.1 Calculating the Reference Point

Explains how to calculate reference points for timing measurements.

14.5 Layout Instructions

Offers guidance on placing and routing CPU interface components.

Section 15. SDRAM Interface Design Considerations

15.1 Interface Connectivity

15.4 Timing Requirements

Details timing requirements for SDRAM interface signals.

15.4.2 Data Timing

Explains timing for SDRAM data bus signals.

15.5 Layout Instructions

Provides guidance on placement and routing for SDRAM systems.

Section 16. PCI Interface Design Considerations

16.1 Interface Connectivity

16.4 Timing Requirements

Details AC timings for PCI interfaces.

Section 17. Ethernet Interface Design Considerations

17.1 Interface Connectivity

17.4 Timing Requirements

Details AC timings for RMII specifications.

17.5 Layout Instructions

Section 18. Power Supply

18.1 De-coupling Recommendations

Recommends decoupling capacitors for power supply noise management.

Section 20. Reset

20.1 Reset Configurations

Section 21. Bringing Up the System (Debugging)

Appendix D. Big and Little Endian Support

D.1 Internal Register

D.4 Swapping Options

Marvell GT-64260A Specifications

General

Cores	1
Bus Interface	PCI
Operating Voltage	3.3V
PCI Bus Speed	66 MHz
Memory Interface	SDRAM
I/O Interfaces	UART, I2C, GPIO
Integrated Peripherals	Interrupt Controller
Operating Temperature	0°C to 70°C