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Marvell Integrated Controller 88F6281 - User Manual

Marvell Integrated Controller 88F6281
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Marvell. Moving Forward Faster
Doc. No. MV-S104859-U0, Rev. E
December 2, 2008, Preliminary
Document Classification: Proprietary Information
Cover
88F6281
Integrated Controller
Hardware Specifications

Table of Contents

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Summary

88 F6281 Integrated Controller Hardware Specifications

Document Conventions

PRODUCT OVERVIEW

FEATURES

Sheeva CPU Core

Details on the 32-bit ARMv5TE-compliant CPU core with MMU and L1/L2 cache.

DDR2 SDRAM Controller

Specifications for the 16-bit DDR2 SDRAM interface up to 800 MHz.

PCI Express Interface (x1)

Details on the x1 PCI Express interface with integrated PHY.

Gigabit Ethernet Ports

Information on the two Gigabit Ethernet MAC ports supporting 10/100/1000 Mbps.

USB 2.0 Port

Specifications for the USB 2.0 port with integrated PHY.

SATA Interface

Details on the SATA II PHYs supporting 3 Gbps SATA II.

Preface

About this Document

Overview of the datasheet's purpose and scope for system designers.

Pin and Signal Descriptions

1.1 Pin Logic

Pin logic diagram illustrating the 88F6281's pin connections.

1.2 Pin Descriptions

Detailed functional description of each pin and its attributes.

1.2.1 Power Supply Pins

Voltage levels for various interface and power supply pins.

1.2.3 DDR SDRAM Interface Pin Assignments

Pin assignments for the DDR SDRAM interface.

1.2.4 PCI Express Interface Pin Assignments

Pin assignments for the PCI Express interface.

1.2.5 SATA Interface Pin Assignments

Pin assignments for the SATA ports.

1.2.6 Gigabit Ethernet Port Interface Pin Assignments

Pin assignments for the Gigabit Ethernet ports.

1.2.8 USB 2.0 Interface Pin Assignments

Pin assignments for the USB 2.0 interface.

1.3 Internal Pull-up and Pull-down Pins

Information on internal pull-up and pull-down resistors on device pins.

Unused Interface Strapping

Pin Multiplexing

4.1 Multi-Purpose Pins Functional Summary

Summary of functionalities assignable to the 50 Multi-Purpose Pins.

Clocking

5.1 Spread Spectrum Clock Generator (SSCG)

Configuration and function of the Spread Spectrum Clock Generator.

System Power Up;Down and Reset Settings

6.1 Power-Up;Down Sequence Requirements

Guidelines for device power-up sequence and voltage requirements.

6.2 Hardware Reset

Information on the device's hardware reset mechanism and pins.

6.3 PCI Express Reset

Details on PCI Express reset types and internal chip reset triggers.

6.5 Pins Sample Configuration

Configuration of pins sampled during SYSRSTn de-assertion.

6.7 Boot Sequence

Procedure describing the boot sequence after reset assertion.

JTAG Interface

7.1 TAP Controller

Description of the Test Access Port (TAP) controller and its states.

7.2 Instruction Register

Details on the 4-bit Instruction Register and supported instructions.

Electrical Specifications (Preliminary)

8.1 Absolute Maximum Ratings

Specifies the extreme limits to which the device can be exposed.

8.2 Recommended Operating Conditions

Defines the operational voltage and temperature ranges for the device.

8.5 DC Electrical Specifications

DC electrical characteristics for various interfaces.

8.6 AC Electrical Specifications

AC timing specifications for various interfaces.

8.7 Differential Interface Electrical Characteristics

Electrical characteristics for differential interfaces like PCIe, SATA, USB.

Thermal Data (Preliminary)

Package

Part Order Numbering;Package Marking

11.1 Part Order Numbering

Scheme for generating part order numbers for the 88F6281.

11.2 Package Marking

Sample commercial package marking and pin 1 location.

Revision History

Marvell Integrated Controller 88F6281 Specifications

General IconGeneral
ManufacturerMarvell
Model88F6281
ArchitectureARM
CPU Speed1.2 GHz
Cores1
Memory SupportDDR2/DDR3
Memory Interface32-bit
USB2 x USB 2.0
Ethernet2 x Gigabit Ethernet
Storage InterfaceSATA II
PCIePCIe x1
PackageBGA

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