Marvell Integrated Controller 88F6281 - Figure 38: SDIO Host in High Speed Mode Output AC Timing Diagram; Figure 39: SDIO Host in High Speed Mode Input AC Timing Diagram

88F6281
Hardware Specifications
Doc. No. MV-S104859-U0 Rev. E Copyright © 2008 Marvell
Page 114 Document Classification: Proprietary Information December 2, 2008, Preliminary
8.6.13.3 Secure Digital Input/Output (SDIO) AC Timing Diagrams
Figure 38: SDIO Host in High Speed Mode Output AC Timing Diagram
Figure 39: SDIO Host in High Speed Mode Input AC Timing Diagram
DAT,
CMD
VIH(min)
VIL(max)
CLK
VIH(min)
VIL(max)
tWHtWL
tDOVB tDOVA
VDDIO/2
DAT,
CMD
VIH(min)
VIL(max)
CLK
VIH(min)
VIL(max)
tWHtWL
tISU
tIHD
VDDIO/2