Marvell Integrated Controller 88F6281 - Table 22: Precise Timing Protocol (PTP) Interface Signal Assignment

Pin and Signal Descriptions
Pin Descriptions
Copyright © 2008 Marvell Doc. No. MV-S104859-U0 Rev. E
December 2, 2008, Preliminary Document Classification: Proprietary Information Page 47
1.2.20 Precise Timing Protocol (PTP) Interface
Note
All of the PTP signals are multiplexed on the MPP pins (see Section 4, Pin Multiplexing,
on page 51
).
Table 22: Precise Timing Protocol (PTP) Interface Signal Assignment
Pin Name
I/O
Pin Type Power Rail
Description
PTP_CLK I CMOS VDDO PTP Clock
PTP_EVENT_REQ I CMOS VDDO Trigger generation to the PTP core.
PTP_TRIG_GEN O CMOS VDDO Trigger generated by the PTP core.