Marvell Integrated Controller 88F6281 - Table 52: MII;MMII MAC Mode AC Timing Table; Figure 14: MII;MMII MAC Mode Test Circuit; Figure 15: MII;MMII MAC Mode Output Delay AC Timing Diagram

Electrical Specifications
AC Electrical Specifications
Copyright © 2008 Marvell Doc. No. MV-S104859-U0 Rev. E
December 2, 2008, Preliminary Document Classification: Proprietary Information Page 97
8.6.5 Media Independent Interface/Marvell Media Independent
Interface (MII/MMII) AC Timing
8.6.5.1 MII/MMII MAC Mode AC Timing Table
Table 52: MII/MMII MAC Mode AC Timing Table
8.6.5.2 MII/MMII MAC Mode Test Circuit
Figure 14: MII/MMII MAC Mode Test Circuit
8.6.5.3 MII/MMII MAC Mode AC Timing Diagrams
Figure 15: MII/MMII MAC Mode Output Delay AC Timing Diagram
Description Symbol Min Max Units Notes
Data input setup relative to RX_CLK rising edge tSU 3.5 - ns -
Data input hold relative to RX_CLK rising edge tHD 2.0 - ns -
Data output delay relative to MII_TX_CLK rising edge tOV 0.0 10.0 ns 1
Note s:
General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified.
1. For all signals, the load is CL = 5 pF.
CL
Test Point
MII_TX_CLK
TXD, TX_EN, TX_ER
Vih(min)
Vil(max)
Vih(min)
Vil(max)
TOV