Marvell Integrated Controller 88F6281 - Figure 29: Inter-IC Sound (I2 S) Output Delay AC Timing Diagram; Figure 30: Inter-IC Sound (I2 S) Input AC Timing Diagram

88F6281
Hardware Specifications
Doc. No. MV-S104859-U0 Rev. E Copyright © 2008 Marvell
Page 108 Document Classification: Proprietary Information December 2, 2008, Preliminary
8.6.10.3 Inter-IC Sound (I
2
S) AC Timing Diagrams
Figure 29: Inter-IC Sound (I
2
S) Output Delay AC Timing Diagram
Figure 30: Inter-IC Sound (I
2
S) Input AC Timing Diagram
I2SBCLK
I2SDO,
I2SLRCLK
VIH(min)
VIH(min)
VIL(max)
tODmin
tODmax
VIL(max)
tCHtCL
I2SDI
VIH(min)
VIL(max)
tSU
tHO
I2SBCLK
VIH(min)
VIL(max)
tCHtCL