Marvell Integrated Controller 88F6281 - Table 13: NAND Flash Interface Pin Assignment

88F6281
Hardware Specifications
Doc. No. MV-S104859-U0 Rev. E Copyright © 2008 Marvell
Page 36 Document Classification: Proprietary Information December 2, 2008, Preliminary
1.2.11 NAND Flash Interface Pin Assignment
Table 13: NAND Flash Interface Pin Assignment
Pin Name I/O Pin
Type
Power
Rail
Description
NF_IO[7:0] I/O CMOS VDDO Data Input/Output
Used to output command, address and data, and to input data
during read operations.
NOTE: All of the NF_IO pins are multiplexed on the MPP pins
(see Section 4, Pin Multiplexing, on page 51)
NF_CLE O CMOS VDDO Command Latch Enable
Controls the activating path for commands sent to the command
register.
NF_ALE O CMOS VDDO Address Latch Enable
Controls the activating path for the address to the internal
address registers.
NF_CEn O CMOS VDDO Chip Enable
Controls the device selection.
NF_REn O CMOS VDDO Read Enable
Controls the serial data-in.
NF_WEn O CMOS VDDO Write Enable
Controls writes to the NF_IO[7:0] ports.