Electrical Specifications
AC Electrical Specifications
Copyright © 2008 Marvell Doc. No. MV-S104859-U0 Rev. E
December 2, 2008, Preliminary Document Classification: Proprietary Information Page 103
8.6.8 Two-Wire Serial Interface (TWSI) AC Timing
8.6.8.1 TWSI AC Timing Table
Table 55: TWSI Master AC Timing Table
Table 56: TWSI Slave AC Timing Table
Description Symbol Min Max Units Notes
SCK clock frequency fCK kHz 1
SCK minimum low level w idth tLOW 0.47 - tCK 2
SCK minimum high level w idth tHIGH 0.40 - tCK 2
SDA input setup time relative to SCK rising edge tSU 250.0 - ns -
SDA input hold time relative to SCK falling edge tHD 0.0 - ns -
SDA and SCK rise time tr - 1000.0 ns 2, 3
SDA and SCK fall time tf - 300.0 ns 2, 3
SDA output delay relative to SCK falling edge tOV 0.0 0.4 tCK 2
Note s:
General comment: All values referred to VIH(min) and VIL(max) levels, unless otherw ise specified.
General comment: tCK = 1/fCK.
1. See "Reference Clocks" table for more details.
2. For all signals, the load is CL = 100 pF, and RL value can be 500 ohm to 8 kilohm.
3. Rise time measured from VIL(max) to VIH(min), fall time measured from VIH(min) to VIL(max).
See note 1
Min Max
SCK minimum low level w idth tLOW 4.7 - us 1
SCK minimum high level w idth tHIGH 4.0 - us 1
SDA input setup time relative to SCK rising edge tSU 250.0 - ns -
SDA input hold time relative to SCK falling edge tHD 0.0 - ns -
SDA and SCK rise time tr - 1000.0 ns 1, 2
SDA and SCK fall time tf - 300.0 ns 1, 2
SDA output delay relative to SCK falling edge tOV 0.0 4.0 us 1
Note s:
General comment: All values referred to VIH(min) and VIL(max) levels, unless otherw ise specified.
1. For all signals, the load is CL = 100 pF, and RL value can be 500 ohm to 8 kilohm.
2. Rise time measured from VIL(max) to VIH(min), fall time measured from VIH(min) to VIL(max).
Note s
100 kHz
Description Symbol Units
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