Marvell Integrated Controller 88F6281 - Figure 7: SDRAM DDR2 Interface Address and Control AC Timing Diagram; Figure 8: SDRAM DDR2 Interface Read AC Timing Diagram

88F6281
Hardware Specifications
Doc. No. MV-S104859-U0 Rev. E Copyright © 2008 Marvell
Page 92 Document Classification: Proprietary Information December 2, 2008, Preliminary
Figure 7: SDRAM DDR2 Interface Address and Control AC Timing Diagram
Figure 8: SDRAM DDR2 Interface Read AC Timing Diagram
ADDRESS/
CONTROL
tIPW
tAOVB tAOVA
CLKn
CLK
tCLtCH
tDHI
tDSI
DQ
DQS
DQSn