MSI Z68A-GD65 series - Chapter 3 BIOS Setup

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Englsh
EIST
The Enhanced Intel SpeedStep technology allows you to set the performance level of
the mcroprocessor whether the computer s runnng on battery or AC power. Ths 󰘰eld
wll appear after you nstalled the CPU whch supports speedstep technology.
Intel Turbo Boost
Ths tem wll appear when you nstall a CPU wth Intel Turbo Boost technology. Ths
tem s used to enable/ dsable Intel Turbo Boost technology. It can scale processor
frequency hgher dynamcally when applcatons demand more performance and TDP
headroom exsts. It also can delver seamless power scalablty (Dynamcally scale up,
Speed-Step Down). It s the Intel newly technology wthn newly CPU.
DRAM Frequency
Ths tem allows you to adjust the DRAM frequency. Please note the overclockng
behavor s not guaranteed.
Adjusted DRAM Frequency
It shows the adjusted DRAM frequency. Read-only.
DRAM Tmng Mode
Select whether DRAM tmng s controlled by the SPD (Seral Presence Detect)
EEPROM on the DRAM module. Settng to [Auto] enables DRAM tmngs and the
followng “Advanced DRAM Con󰘰guraton” sub-menu to be determned by BIOS based
on the con󰘰guratons on the SPD. Selectng [Lnk] or [Unlnk] allows users to con󰘰gure
the DRAM tmngs for each channel and the followng related “Advanced DRAM
Con󰘰guraton” sub-menu manually.
Advanced DRAM Con󰘰guraton
Press <Enter> to enter the sub-menu.
Command Rate
Ths settng controls the DRAM command rate.
tCL
Ths controls the CAS latency, whch determnes the tmng delay (n clock cycles)
before SDRAM starts a read command after recevng t.
tRCD
When DRAM s refreshed, both rows and columns are addressed separately. Ths
setup tem allows you to determne the tmng of the transton from RAS (row address
strobe) to CAS (column address strobe). The less the clock cycles, the faster the
DRAM performance.
tRP
Ths settng controls the number of cycles for Row Address Strobe (RAS) to be
allowed to precharge. If nsu󰘲cent tme s allowed for the RAS to accumulate ts
charge before DRAM refresh, refreshng may be ncomplete and DRAM may fal
to retan data. Ths tem apples only when synchronous DRAM s nstalled n the
system.
tRAS
Ths settng determnes the tme RAS takes to read from and wrte to memory cell.
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