Nippon DENON DCD-3000 User Manual

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PinNo. | Symbol | VO Tenminal Function
at | Voo —_| Digital power supply.
42_ | ASYE 1_| Asymmetry circuit ON/OFF (L=OFF, H=ON).
43 | Psst 1__| Audio data output mode shifting input. L to serial output, H to parallel output.
44 | WOCK © | 48-bit stot D/A interface. Word clock I=2Fs.
45__| LRCK (| 48-bit siot D/A interlace. LR clock =F.
46__| DAIS © | DAt6 output at PSSL=1. Serial data of 48-bit slot at PSSL=0.
z 47__| DAIS © _| DATS output at PSSL=1. Bit clock of 48-bit slot at PSSL=0.
48 Data © | DAt4 output at PSSL=1, Serial data of 64-bi sio! at PSSL=0.
49 | DAIS © | DATS output at PSSL=1, Bit clock of 64-bit slot at PSSL=0.
50 | DAI2 © _|_DAt2 output at PSSL=1. LR clock of 64-bit slot at PSSL=0.
51 | DAT © | DA‘ output at PSSL=1. GTOP output at PSSL=0.
52 | DAIO © | DAt0 cutput at PSSL=1. XUGF output at PSSL=0.
53 | DA0S © _ | DA09 output at PSSL=1. XPLCK output at PSSL=0.
54 | DAGB © | 0A08 output at PSSL=1. GFS output at PSSL=0.
55 | DAO? © | DA07 output at PSSL=1. RFCK output at PSSL-0.
56 | DADS © | BA06 output at PSSL=1. C2PO output at PSSL=0,
57 | DAOS © | DA0s output at PSSL=1. XRAOF output at PSSL=0.
58 | DAO4 © | 0A04 output at PSSL=1. MNTS output at PSSL=0.
‘DAS © | DA0s output at PSSL=1, MNT2 output at PSSL-0.
= DAO ° DA02 output at PSSL=1. MNT1 output at PSSL=0.
° DA01 output at PSSL=1. MNTO output at PSSL=0.
82 XTAL E X'tal oscillation circuit input. 16.9344MHz or 33.8688MHz input.
63 XTAO- ° X'tal oscillation circuit output.
64 | XTSL \__| Xtal selection input terminal. L at X'tal for 16.9344MHz, at 33.8688MHz tums to H.
65 | Ves —_| Digital GND.
66 FSTI 1 2/3 divided input of terminals 62 and 63.
67 | FSTO O _| 2/8 divided input of terminals 62 and 63. Unvarying by variable pitch,
68 C4M ° 4.2366MHz output. Simultaneously varies when variable pitched,
69 | Ciom © _|16.934¢MHz output. Simultaneously varies when variable pitched,
70 Mb2 4 Diglta!-out ON/OFF control terminal (L=<OFF, H=ON).
‘0 _| Digtal-out output terminal.
9 Emphasis mode output of playback disc (t at without emphasis, H at emphasized).
ie) WECK output,
Qo Subcode syne output terminal (H at detecting either one of SO or SI subcode sync).
7% $Bs0 C) Serial output of sub PW,
76 EXCK | Clock input for SBSO read out.
7 SQso © _| Subd 80-bit output. PCM peak data, level data 16-bit output.
78 sack 4 Clock input for SQSO read out.
79 MUTE i Mute shifting terminal (H to mute).
80 SENS: ° SENS output. Outputs to CPU.
a1 | XAST 1__[ System reset (L to reset).
@2__| DIRC 1 [Used for at track jump.
83 | SCLK 1 | Clock for SENS serial data reading.
84 | DFSW 1__|_DFCT shifting terminal (H to DFCT countermeasure circuit OFF).
85__| ATSK 1_| Anti-shook terminal.
86 | DATA (| Serial data input from CPU.
87__| XLAT (| Latch input trom CPU.
@8 | CLOK [Serial data transfer clock input from CPU.
89 | cour | _Number of track count signal output.
90 __| Yoo —_| Digital power supply.
91 | MIRR 0 | Mirror signal output.
92” | DFOT 0 | Detect signal ouput.
93 | FOK 0 | Focus OK output.
a4 | FSW © _| Output fitter shitting output of spindle motor.
95 | MON [ON/OFF control output of spindle motor.
96 | MDP 0 | Servo control of spindie motor.
o7__| MDs © | Serva control of spindle motor.
98 | LOCK © __| Sampling GFS with 480H2 and outputs H at GFS is H. Outputs L when continuously 8 times L.
99 | SSTP |__| Terminal for inner most circle detection signal of disc.
100 | SFDR O__| Sled drive output.
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Nippon DENON DCD-3000 Specifications

General

Brand	Nippon
Model	DENON DCD-3000
Category	CD Player
Language	English