Name: Nuvoton ARM Cortex NuMicro M451 Series
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M451

May. 4, 2018 Page 1 of 1006 Rev.2.08

M451 SERIES TECHNICAL REFERENCE MANUAL

ARM

Cortex

-M

32-bit Microcontroller

NuMicro

Family

M451 Series

Technical Reference Manual

The information described in this document is the exclusive intellectual property of

Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.

Nuvoton is providing this document only for reference purposes of NuMicro microcontroller based

system design. Nuvoton assumes no responsibility for errors or omissions.

All data and specifications are subject to change without notice.

For additional information or questions, please contact: Nuvoton Technology Corporation.

www.nuvoton.com

Table of Contents2
General Description19
Table 1-1 Key Features Support Table19
Features21
Numicro ® M451 Features21
Abbreviations27
Table 3-1 List of Abbreviations28
Parts Information List and Pin Configuration29
Numicro M451 Selection Guide29
Numicro ® M451 Naming Rule29
Figure 4.1-1 Numicro M451 Selection Code29
Numicro ® M451 Base Series Selection Guide30
Numicro ® M451M Series (M051 Pin Compatible) Selection Guide31
Numicro ® M452 USB Series Selection Guide32
Numicro ® M453 CAN Series (CAN+USB) Selection Guide33
Pin Configuration34
Numicro ® M451 Base Series LQFP48 Pin Diagram34
Figure 4.2-1 Numicro ® M451 Base Series LQFP 48-Pin Diagram34
Numicro ® M451 Base Series LQFP64 Pin Diagram35
Figure 4.2-2 Numicro M451 Base Series LQFP 64-Pin Diagram35
Numicro ® M451 Base Series LQFP100 Pin Diagram36
Figure 4.2-3 Numicro M451 Base Series LQFP 100-Pin Diagram36
Numicro ® M451M Series (M051 Pin Compatible) LQFP48 Pin Diagram37
Figure 4.2-4 Numicro ® M451M Base Series (Pin Compatible with M051) LQFP 48-Pin Diagram37
Numicro ® M451M Series (M058S Pin Compatible) LQFP64 Pin Diagram38
M451M Base Series (Pin Compatible with M058S) LQFP 64-Pin Diagram38
Numicro ® M452 USB Series LQFP48 Pin Diagram39
Figure 4.2-6 Numicro39
M451 USB Series LQFP 48-Pin Diagram (M452LG/M452LE Device Only)39
Figure 4.2-7 Numicro M451 USB Series LQFP 48-Pin Diagram (M452LD/M452LC Device Only)40
Numicro ® M452 USB Series LQFP64 Pin Diagram41
Figure 4.2-8 Numicro M451 USB Series LQFP 64-Pin Diagram (M452RG/M452RE Device Only)41
Figure 4.2-9 Numicro ® M451 USB Series LQFP 64-Pin Diagram (M452RD Device Only)42
Numicro ® M452 USB Series LQFP100 Pin Diagram43
Figure 4.2-10 Numicro M451 USB Series LQFP 100-Pin Diagram (M452VG/M452VE Device Only)43
Numicro ® M453 CAN Series (CAN+USB) LQFP48 Pin Diagram44
Figure 4.2-11 Numicro M451 CAN Series (CAN+USB) LQFP 48-Pin Diagram (M453LG/M453LE Device Only)44
Figure 4.2-12 Numicro M451 CAN Series (CAN+USB) LQFP 48-Pin Diagram (M453LD/M453LC Device Only)45
Numicro ® M453 CAN Series (CAN+USB) LQFP64 Pin Diagram46
Figure 4.2-13 Numicro M451 CAN Series (CAN+USB) LQFP 64-Pin Diagram (M453RG/M453RE Device Only)46
Figure 4.2-14 Numicro M451 CAN Series (CAN+USB) LQFP 64-Pin Diagram (M453RD Device Only)47
Numicro M453 CAN Series (CAN+USB) LQFP100 Pin Diagram48
Figure 4.2-15 Numicro M451 CAN Series (CAN+USB) LQFP 100-Pin Diagram (M453VG/M453VE Device Only)48
Figure 4.2-16 Numicro M451 CAN Series (CAN+USB) LQFP 100-Pin Diagram (M453VD Device Only)49
Pin Description50
M451 Base Series LQFP48 Pin Description50
M451 Base Series LQFP64 Pin Description58
M451 Base Series LQFP100 Pin Description68
M451M Series (M051 Pin Compatible) LQFP48 Pin Description81
M451M Series (M058S Pin Compatible) LQFP64 Pin Description89
M452 USB Series LQFP48 Pin Description98
M452 USB Series LQFP64 Pin Description105
M452 USB Series LQFP100 Pin Description114
M453 CAN Series(CAN+USB) LQFP48 Pin Description127
M453 CAN Series(CAN+USB) LQFP64 Pin Description135
M453 CAN Series(CAN+USB) LQFP100 Pin Description144
GPIO Multi-Function Pin Summary157
Table 4-1 M451 GPIO Multi-Function Table166
Block Diagram167
Numicro M451 Block Diagram167
Figure 5.1-1 Numicro M45Xg/M45Xe Block Diagram167
Figure 5.1-2 Numicro M45Xd/M45Xc Block Diagram168
Functional Description169
ARM ® Cortex ® -M4 Core169
Figure 6.1-1 Cortex ® -M4 Block Diagram169
System Manager172
Overview172
System Reset172
Figure 6.2-1 System Reset Sources173
Table 6-1 Reset Value of Registers175
Figure 6.2-2 Nreset Reset Waveform176
Figure 6.2-3 Power-On Reset (POR) Waveform176
Figure 6.2-4 Low Voltage Reset (LVR) Waveform177
Figure 6.2-5 Brown-Out Detector (BOD) Waveform178
Power Modes and Wake-Up Sources179
Figure 6.2-6 Power Mode State Machine179
Table 6-2 Power Mode Difference Table179
System Power Distribution181
Table 6-3 Clocks in Power Modes181
Table 6-4 Condition of Entering Power-Down Mode Again181
Figure 6.2-7 Numicro M451 Power Distribution Diagram182
System Memory Map183
Table 6-5 Address Space Assignments for On-Chip Controllers185
SRAM Memory Organization186
Figure 6.2-8 SRAM Block Diagram186
Figure 6.2-9 SRAM Memory Organization (M45Xg/M45Xe)187
Figure 6.2-10 SRAM Memory Organization (M45Xd/M45Xc)188
Register Map190
Register Description192
System Timer (Systick)231
Nested Vectored Interrupt Controller (NVIC)235
Table 6-6 Exception Model236
Table 6-7 Interrupt Number Table238
System Control Register258
Table 6-8 Priority Grouping262
Clock Controller267
Overview267
Figure 6.3-1 Clock Generator Global View Diagram268
Clock Generator269
Figure 6.3-2 Clock Generator Block Diagram269
System Clock and Systick Clock270
Figure 6.3-3 System Clock Block Diagram270
Peripherals Clock271
Figure 6.3-4 HXT Stop Protect Procedure271
Figure 6.3-5 Systick Clock Control Block Diagram271
Power-Down Mode Clock272
Clock Output272
Figure 6.3-6 Clock Source of Clock Output272
Figure 6.3-7 Clock Output Block Diagram273
Register Map274
Register Description275
Table 6-9 Power-Down Mode Control Table277
Flash Memeory Controller (FMC)299
Overview299
Features299
Block Diagram300
Figure 6.4-1 Flash Memory Controller Block Diagram300
Functional Description303
Figure 6.4-2 Data Flash Shared with APROM303
Figure 6.4-3 Flash Memory Map308
Figure 6.4-4 System Memory Map with IAP Mode309
Figure 6.4-5 LDROM with IAP Mode310
Figure 6.4-6 APROM with IAP Mode310
Figure 6.4-7 System Memory Map Without IAP Mode311
Figure 6.4-8 Boot Source Selection312
Table 6-10 ISP Command List314
Figure 6.4-9 ISP Procedure Example315
Figure 6.4-10 ISP 32-Bit Programming Procedure317
Figure 6.4-11 ISP 64-Bit Programming Procedure317
Figure 6.4-12 Multi-Word Programming Time318
Figure 6.4-13 Firmware in SRAM for Multi-Word Programming319
Figure 6.4-14 Multi-Word Programming Flow320
Figure 6.4-15 Fast Flash Programming Verification Flow321
Figure 6.4-16 Verification Flow322
Figure 6.4-17 Checksum for KB Calculation322
Figure 6.4-18 Checksum Calculation Flow324
Register Map325
Register Description326
External Bus Interface (EBI)343
Overview343
Features343
Block Diagram344
Basic Configuration344
Functional Description344
Figure 6.5-1 EBI Block Diagram344
Figure 6.5-2 Connection of 16-Bit EBI Data Width with 16-Bit Device345
Figure 6.5-3 Connection of 8-Bit EBI Data Width with 8-Bit Device346
Figure 6.5-4 Timing Control Waveform for 16-Bit Data Width348
Figure 6.5-5 Timing Control Waveform for 8-Bit Data Width349
Figure 6.5-6 Timing Control Waveform for Insert Idle Cycle350
Register Map351
Register Description352
General Purpose I/O (GPIO)356
Overview356
Features356
Block Diagram357
Basic Configuration357
Figure 6.6-1 GPIO Controller Block Diagram357
Functional Description358
Figure 6.6-2 Push-Pull Output358
Figure 6.6-3 Open-Drain Output358
Figure 6.6-4 Quasi-Bidirectional I/O Mode359
Register Map360
Register Description363
PDMA Controller (PDMA)378
Overview378
Features378
Block Diagram378
Figure 6.7-1 PDMA Controller Block Diagram378
Basic Configuration379
Functional Description379
Figure 6.7-2 Descriptor Table Entry Structure379
Table 6-11 Channel Priority Table (M45Xg/M45Xe Only)380
Table 6-12 Channel Priority Table (M45Xd/M45Xc Only)380
Figure 6.7-3 Basic Mode Finite State Machine381
Figure 6.7-4 Descriptor Table Link List Structure382
Figure 6.7-5 Scatter-Gather Mode Finite State Machine382
Figure 6.7-6 Example of Single Transfer Type and Burst Transfer Type in Basic Mode384
Register Map385
Register Description387
Timer Controller (TMR)416
Overview416
Features416
Block Diagram417
Figure 6.8-1 Timer Controller Block Diagra417
Basic Configuration418
Functional Description418
Figure 6.8-2 Clock Source of Timer Controller418
Figure 6.8-3 Continuous Counting Mode420
Register Map423
Register Description425
PWM Generator and Capture Timer (PWM)435
Overview435
Features435
Block Diagram437
Figure 6.9-1 PWM Generator Overview Block Diagram437
Figure 6.9-2 PWM System Clock Source Control437
Figure 6.9-3 PWM Clock Source Control438
Table 6-13 PWM System Clock Source Control Registers Setting Table438
Figure 6.9-4 PWM Independent Mode Architecture Diagram439
Basic Configuration440
Functional Description440
Figure 6.9-5 PWM Complementary Mode Architecture Diagram440
Figure 6.9-6 PWM_CH0 Prescaler Waveform441
Figure 6.9-7 PWM up Counter Type441
Figure 6.9-8 PWM down Counter Type442
Figure 6.9-9 PWM Up-Down Counter Type442
Figure 6.9-10 PWM CMPDAT Events in Up-Down Counter Type443
Figure 6.9-11 PWM Double Buffering Illustration444
Figure 6.9-12 Period Loading in Up-Count Mode445
Figure 6.9-13 Immediately Loading in Up-Count Mode446
Figure 6.9-14 Window Loading in Up-Count Mode447
Figure 6.9-15 Center Loading in Up-Down-Count Mode448
Figure 6.9-16 PWM One-Shot Mode Output Waveform449
Figure 6.9-17 PWM Pulse Generation450
Figure 6.9-18 PWM 0% to 100% Pulse Generation450
Table 6-14 PWM Pulse Generation Event Priority for Up-Counter450
Figure 6.9-19 PWM Independent Mode Waveform451
Table 6-15 PWM Pulse Generation Event Priority for Down-Counter451
Table 6-16 PWM Pulse Generation Event Priority for Up-Down-Counter451
Figure 6.9-20 PWM Complementary Mode Waveform452
Figure 6.9-21 PWM Group Function Waveform453
Figure 6.9-22 PWM SYNC_IN Noise Filter Block Diagram453
Figure 6.9-23 PWM Counter Synchronous Function Block Diagram454
Figure 6.9-24 PWM Synchronous Function with SINSRC=0455
Figure 6.9-25 PWM_CH0 Output Control in Independent Mode455
Figure 6.9-26 PWM_CH0 and PWM_CH1 Output Control in Complementary Mode456
Figure 6.9-27 Dead-Time Insertion457
Figure 6.9-28 Illustration of Mask Control Waveform457
Figure 6.9-29 Brake Noise Filter Block Diagram458
Figure 6.9-30 Brake Block Diagram for PWM_CH0 and PWM_CH1 Pair459
Figure 6.9-31 Edge Detector Waveform for PWM_CH0 and PWM_CH1 Pair460
Figure 6.9-32 Level Detector Waveform for PWM_CH0 and PWM_CH1 Pair460
Figure 6.9-33 Brake Source Block Diagram461
Figure 6.9-34 Brake System Fail Block Diagram461
Figure 6.9-35 Initial State and Polarity Control with Rising Edge Dead-Time Insertion462
Figure 6.9-36 PWM_CH0 and PWM_CH1 Pair Accumulate Interrupt Waveform463
Figure 6.9-37 PWM_CH0 and PWM_CH1 Pair Interrupt Architecture Diagram464
Figure 6.9-38 PWM_CH0 and PWM_CH1 Pair Trigger EADC Block Diagram465
Figure 6.9-39 PWM Trigger EADC in Up-Down Counter Type Timing Waveform466
Figure 6.9-40 PWM_CH0 and PWM_CH1 Pair Trigger DAC Block Diagram466
Figure 6.9-41 PWM_CH0 Capture Block Diagram467
Figure 6.9-42 Capture Operation Waveform468
Figure 6.9-43 Capture PDMA Operation Waveform of Channel 0469
Register Map470
Register Description476
Watchdog Timer (WDT)540
Overview540
Features540
Block Diagram540
Clock Control540
Figure 6.10-1 Watchdog Timer Block Diagram540
Basic Configuration541
Functional Description541
Figure 6.10-2 Watchdog Timer Clock Control541
Figure 6.10-3 Watchdog Timer Time-Out Interval and Reset Period Timing542
Table 6-17 Watchdog Timer Time-Out Interval Period Selection542
Register Map543
Register Description544
Window Watchdog Timer (WWDT)547
Overview547
Features547
Block Diagram547
Figure 6.11-1 WWDT Block Diagram547
Clock Control548
Basic Configuration548
Functional Description548
Figure 6.11-2 WWDT Clock Control548
Figure 6.11-3 WWDT Reset and Reload Behavior549
Table 6-18 WWDT Prescaler Value Selection549
Table 6-19 CMPDAT Setting Limitation550
Register Map551
Register Description552
Real Time Clock (RTC)557
Overview557
Features557
Block Diagram558
Basic Configuration558
Functional Description558
Figure 6.12-1 RTC Block Diagram558
Table 6-20 RTC Control Registers Access Attribute559
Figure 6.12-2 Backup I/O Control Diagram564
Register Map565
Register Description567
UART Interface Controller (UART)590
Overview590
Features590
Block Diagram591
Table 6-21 Numicro M451 Series UART Feature591
Figure 6.13-1 UART Clock Control Diagram592
Figure 6.13-2 UART Block Diagram593
Basic Configuration594
Functional Description594
Table 6-22 UART Interface Controller Pin594
Table 6-23 UART Controller Baud Rate Equation Table594
Table 6-24 UART Controller Baud Rate Parameter Setting Example Table595
Figure 6.13-3 Auto-Baud Rate Measurement596
Table 6-25 UART Controller Baud Rate Register Setting Example Table596
Figure 6.13-4 Transmit Delay Time Operation597
Figure 6.13-5 UART Ncts Wake-UP Case1598
Figure 6.13-6 UART Ncts Wake-UP Case2598
Figure 6.13-7 UART RX Data Wake-Up598
Table 6-26 UART Controller Interrupt Source and Flag List600
Table 6-27 UART Line Control of Word and Stop Length Setting600
Table 6-28 UART Line Control of Parity Bit Setting600
Figure 6.13-8 Auto-Flow Control Block Diagram601
Figure 6.13-9 UART Ncts Auto-Flow Control Enabled602
Figure 6.13-10 UART Nrts Auto-Flow Control Enabled602
Figure 6.13-11 UART Nrts Auto-Flow with Software Control603
Figure 6.13-12 Irda Control Block Diagram603
Figure 6.13-13 Irda TX/RX Timing Diagram604
Figure 6.13-14 Structure of LIN Frame605
Figure 6.13-15 Structure of LIN Byte605
Table 6-29 LIN Header Selection in Master Mode606
Figure 6.13-16 Break Detection in LIN Mode607
Figure 6.13-17 LIN Frame ID and Parity Format608
Figure 6.13-18 LIN Sync Field Measurement610
Figure 6.13-19 UART_BAUD Update Sequence in AR Mode if SLVDUEN Is 1611
Figure 6.13-20 UART_BAUD Update Sequence in AR Mode if SLVDUEN Is 0611
Figure 6.13-21 RS-485 Nrts Driving Level in Auto Direction Mode615
Figure 6.13-22 RS-485 Nrts Driving Level with Software Control615
Figure 6.13-23 Structure of RS-485 Frame616
Register Map617
Register Description619
Smart Card Host Interface (SC)646
Overview646
Features646
Block Diagram646
Figure 6.14-1 SC Clock Control Diagram (4-Bit Pre-Scale Counter in Clock Controller)647
Figure 6.14-2 SC Controller Block Diagram647
Basic Configuration648
Functional Description648
Figure 6.14-3 SC Data Character648
Table 6-30 SC Host Controller Pin Description648
Table 6-31 UART Pin Description648
Figure 6.14-4 SC Activation Sequence649
Figure 6.14-5 SC Warm Reset Sequence650
Figure 6.14-6 SC Deactivation Sequence651
Figure 6.14-7 Basic Operation Flow652
Figure 6.14-8 Initial Character TS653
Figure 6.14-9 SC Error Signal653
Figure 6.14-10 Transmit Direction Block Guard Time Operation655
Table 6-32 Timer2/Timer1/Timer0 Operation Mode655
Figure 6.14-11 Receive Direction Block Guard Time Operation656
Figure 6.14-12 Extended Guard Time Operation656
Register Map657
Register Description658
I 2 C Serial Interface Controller (I 2 C)684
Overview684
Features684
Basic Configuration684
Block Diagram685
Functional Description685
Figure 6.15-1 I 2 C Controller Block Diagram685
Figure 6.15-2 I 2 C Bus Timing685
Figure 6.15-3 I 2 C Protocol686
Figure 6.15-4 START and STOP Conditions688
Figure 6.15-5 Bit Transfer on the I 2 C Bus690
Figure 6.15-6 Acknowledge on the I C Bus690
Figure 6.15-7 Master Transmits Data to Slave691
Figure 6.15-8 Master Reads Data from Slave691
Figure 6.15-9 Control I692
Status692
Figure 6.15-10 Master Transmitter Mode Control Flow693
Figure 6.15-11 Master Receiver Mode Control Flow694
Figure 6.15-12 Save Mode Control Flow695
Figure 6.15-13 GC Mode697
Figure 6.15-14 Arbitration Lost698
Table 6-33 Reserved Smbus Address699
Figure 6.15-15 Bus Management Packet Protocol Diagram Element Key700
Figure 6.15-167-Bit Addressable Device to Host Communication701
Figure 6.15-177-Bit Addressable Device Responds to an ARA701
Figure 6.15-18 Bus Management ALERT Function702
Figure 6.15-19 SM Bus Time out Timing703
Figure 6.15-20 I 2 C Data Shifting Direction707
Table 6-34 I 2 C Status Code Description709
Figure 6.15-21 I 2 C Time-Out Count Block Diagram711
Figure 6.15-22 EEPROM Random Read717
Figure 6.15-23 Protocol of EEPROM Random Read718
Register Map719
Register Description720
Serial Peripheral Interface (SPI)740
Overview740
Features740
Block Diagram741
Figure 6.16-1 SPI Block Diagram (SPI0)741
Figure 6.16-2 SPI Block Diagram (SPI1/2)741
Basic Configuration742
Functional Description743
Figure 6.16-3 SPI Peripheral Clock743
Table 6-35 SPI/I 2 S Interface Controller Pin743
Figure 6.16-4 SPI Master Mode Application Block Diagram744
Figure 6.16-5 SPI Slave Mode Application Block Diagram744
Figure 6.16-632-Bit in One Transaction (Master Mode)745
Figure 6.16-7 Automatic Slave Selection (SSACTPOL = 0, SPI_CYCLE > 0X2)746
Figure 6.16-8 Automatic Selection (SSACTPOL = 0, SPI_CYCLE < 0X3)746
Figure 6.16-9 Byte Reorder Function747
Figure 6.16-10 Timing Waveform for Byte Suspend747
Figure 6.16-11 Two-Bit Transfer Mode System Architecture748
Figure 6.16-12 Two-Bit Transfer Mode Timing (Master Mode)749
Figure 6.16-13 Bit Sequence of Dual Output Mode750
Figure 6.16-14 Bit Sequence of Dual Input Mode750
Figure 6.16-15 Bit Sequence of Quad Output Mode751
Figure 6.16-16 Bit Sequence of Quad Input Mode751
Figure 6.16-17 FIFO Threshold Comparator752
Figure 6.16-18 Transmit FIFO Buffer Example753
Figure 6.16-19 Receive FIFO Buffer Example754
Figure 6.16-20 TX Underflow Event and Slave under Run Event (Slave 3-Wire Mode Disabled)754
Figure 6.16-21 Two-Bit Transfer Mode FIFO Buffer Example755
Figure 6.16-22 TX Underflow Event (Slave 3-Wire Mode Enabled)755
Figure 6.16-23 Slave Mode Bit Count Error756
Figure 6.16-24 Slave Time-Out Event756
Figure 6.16-25 I 2 S Data Format Timing Diagram758
Figure 6.16-26 MSB Justified Data Format Timing Diagram759
Figure 6.16-27 PCM Mode a Timing Diagram759
Figure 6.16-28 PCM Mode B Timing Diagram759
Figure 6.16-29 FIFO Contents for Various I760
Modes760
Timing Diagram761
Figure 6.16-30 SPI Timing in Master Mode761
Figure 6.16-31 SPI Timing in Master Mode (Alternate Phase of Spin_Clk)761
Figure 6.16-32 SPI Timing in Slave Mode762
Figure 6.16-33 SPI Timing in Slave Mode (Alternate Phase of Spin_Clk)762
Programming Examples763
Register Map765
Register Description766
USB Device Controller (USBD)785
Overview785
Features785
Block Diagram786
Basic Configuration786
Functional Description786
Figure 6.17-1 USB Block Diagram786
Figure 6.17-2 NEVWK Interrupt Operation Flow787
Figure 6.17-3 Endpoint SRAM Structure788
Figure 6.17-4 Setup Transaction Followed by Data in Transaction789
Figure 6.17-5 Data out Transfer789
Register Map790
Register Description792
USB 1.1 Host Controller (USBH)808
Overview808
Features808
Block Diagram809
Figure 6.18-1 USB 1.1 Host Controller Block Diagram809
Basic Configuration810
Functional Description810
Register Map812
Register Description814
USB On-The-Go (OTG)845
Overview845
Features845
Block Diagram846
Basic Configuration846
Functional Description846
Figure 6.19-1 USB OTG Block Diagram846
Figure 6.19-2 USB Device Mode847
Figure 6.19-3 USB Host Mode847
Register Map849
Register Description850
Controller Area Network (CAN)858
Overview858
Features858
Basic Configuration858
Block Diagram858
Functional Description859
Figure 6.20-1 CAN Peripheral Block Diagram859
Test Mode861
Figure 6.20-2 CAN Core in Silent Mode861
Figure 6.20-3 CAN Core in Loop Back Mode862
Figure 6.20-4 CAN Core in Loop Back Mode Combined with Silent Mode862
CAN Communications863
Figure 6.20-5 Data Transfer between Ifn Registers and Message865
Table 6-36 Initialization of a Transmit Object867
Table 6-37 Initialization of a Receive Object868
Figure 6.20-6 Application Software Handling of a FIFO Buffer870
Figure 6.20-7 Bit Timing872
Table 6-38 CAN Bit Time Parameters872
Figure 6.20-8 Propagation Time Segment873
Figure 6.20-9 Synchronization on "Late" and "Early" Edges875
Figure 6.20-10 Filtering of Short Dominant Spikes876
Figure 6.20-11 Structure of the CAN Core's CAN Protocol Controller877
Register Map881
Table 6-39 CAN Register Map for each Bit Function886
Register Description887
Table 6-40 Last Error Code891
Table 6-41 Source of Interrupts894
Table 6-42 IF1 and IF2 Message Interface Register897
Table 6-43 Structure of a Message Object in the Message Memory911
CRC Controller (CRC)922
Overview922
Features922
Block Diagram922
Figure 6.21-1 CRC Generator Block Diagram922
Basic Configuration923
Functional Description923
Register Map924
Register Description925
Enhanced 12-Bit Analog-To-Digital Converter (EADC)930
Overview930
Features930
Block Diagram931
Basic Configuration931
Figure 6.22-1 ADC Converter Block Diagram931
Operation Procedure932
Figure 6.22-2 Sample Module 0~3 Block Diagram932
Figure 6.22-3 Sample Module 4~15 Block Diagram933
Figure 6.22-4 Sample Module 16~18 Block Diagram933
Figure 6.22-5 EADC Clock Control934
Figure 6.22-6 Example ADC Conversion Timing Diagram, N=0~18935
Figure 6.22-7 Sample Module Conversion Priority Arbitrator Diagram936
Figure 6.22-8 Specific Sample Module A/D EOC Signal for ADINT0~3 Interrupt937
Figure 6.22-9 STADC De-Bounce Timing Diagram938
Figure 6.22-10 PWM-Triggered ADC Start Conversion938
Figure 6.22-11 External Triggered ADC Start Conversion938
Figure 6.22-12 Conversion Start Delay Timing Diagram939
Figure 6.22-13 A/D Extend Sampling Timing Diagram940
Figure 6.22-14 A/D Conversion Result Monitor Logics Diagram941
Table 6-44 EADC Differential Model Channel Table941
Figure 6.22-15 A/D Controller Interrupts942
Register Map943
Register Description946
Digital to Analog Converter (DAC)973
Overview973
Features973
Block Diagram973
Figure 6.23-1 Digital-To-Analog Converter Block Diagram973
Basic Configuration974
Functional Description974
Figure 6.23-2 Data Holding Register Format974
Figure 6.23-3 DAC Conversion Started by Software Write Trigger975
Figure 6.23-4 DAC Conversion Started by Hardware Trigger Event975
Figure 6.23-5 DAC PDMA Underrun Condition Example976
Figure 6.23-6 DAC Continuous Conversion with Software PDMA Mode977
Figure 6.23-7 DAC Interrupt Source977
Register Map978
Register Description979
Analog Comparator Controller (ACMP)986
Overview986
Features986
Block Diagram987
Figure 6.24-1 Analog Comparator Block Diagram987
Basic Configuration988
Functional Description988
Figure 6.24-2 Comparator Controller Interrupt Sources988
Figure 6.24-3 Comparator Hysteresis Function989
Figure 6.24-4 Comparator Reference Voltage Block Diagram989
Register Map990
Register Description991
Application Circuit998
Electrical Characteristics999
Package Dimensions1000
LQFP 100L (14X14X1.4 MM Footprint 2.0 MM)1000
LQFP 64L (10X10X1.4 MM Footprint 2.0 MM)1001
LQFP 64L (7X7X1.4 MM Footprint 2.0 MM)1002
LQFP 48L (7X7X1.4Mm Footprint 2.0Mm)1003
Revision History1004

Nuvoton ARM Cortex NuMicro M451 Series User Manual

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Brand	Nuvoton
Model	ARM Cortex NuMicro M451 Series
Category	Microcontrollers
Language	English