Nuvoton NuMicro Series

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ML51/ML54/ML56

Sep. 01, 2020 Page 1 of 719 Rev 2.00

ML51/ML54/ML56 SERIES TECHNICAL REFERENCE MANUAL

ML51/ML54/ML56 Series

Technical Reference

Manual

1T 8051

8-bit Microcontroller

NuMicro

Family

ML51/ML54/ML56 Series

Technical Reference Manual

The information described in this document is the exclusive intellectual property of

Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.

Nuvoton is providing this document only for reference purposes of NuMicro

microcontroller based

system design. Nuvoton assumes no responsibility for errors or omissions.

All data and specifications are subject to change without notice.

For additional information or questions, please contact: Nuvoton Technology Corporation.

www.nuvoton.com

Main Page

Table of Contents2
General Description11
Features12
Part Information17
ML51/ML54/ML56 Series Package Type17
ML51/ML54/ML56 Series Selection Guide18
ML51 Series18
ML54 Series21
ML56 Series22
ML51/ML54/ML56 Series Selection Code23
Pin Configuration24
ML51/ML54/ML56 Series Pin Diagram24
Figure 4.1-1 ML51SD1AE Pin Assignment24
Figure 4.1-2 ML54SD1AE / ML56SD1AE Pin Assignment25
Figure 4.1-3 ML51LD1AE Pin Assignment26
Figure 4.1-4 ML54LD1AE / ML56LD1AE Pin Assignment26
Figure 4.1-5 ML54MD1AE / ML56MD1AE Pin Assignment27
Figure 4.1-6 ML51TD1AE / ML51TC0AE / ML51TB9AE Pin Assignment27
Figure 4.1-7 ML51PC0AE / ML51PB9AE Pin Assignment28
Figure 4.1-8 ML51EC0AE / ML51EB9AE Pin Assignment28
Figure 4.1-9 ML51UC0AE / ML51UB9AE Pin Assignment29
Figure 4.1-10 ML51FB9AE Pin Assignment29
Figure 4.1-11 ML51OB9AE Pin Assignment30
Figure 4.1-12 ML51XB9AE Pin Assignment30
Figure 4.1-13 ML51DB9AE Pin Assignment31
Figure 4.1-14 ML51BB9AE Pin Assignment31
ML51/ML54/ML56 Series Multi Function Pin Diagram32
Figure 4.1-15 ML51SD1AE Multi-Function Pin Assignment32
Figure 4.1-16 ML54SD1AE Multi-Function Pin Assignment35
Figure 4.1-17 ML56SD1AE Multi-Function Pin Assignment38
Figure 4.1-18 ML51LD1AE Multi-Function Pin Assignment41
Figure 4.1-19 ML54LD1AE Multi-Function Pin Assignment44
Figure 4.1-20 ML56LD1AE Multi-Function Pin Assignment47
Figure 4.1-21 ML54MD1AE Multi-Function Pin Assignment50
Figure 4.1-22 ML56MD1AE Multi-Function Pin Assignment53
Figure 4.1-23 ML51TD1AE Multi-Function Pin Assignment56
Figure 4.1-24 ML51TC0AE / ML51TB9AE Multi-Function Pin Assignment58
Figure 4.1-25 ML51PC0AE / ML51PB9AE Multi-Function Pin Assignment60
Figure 4.1-26 ML51EC0AE / ML51EB9AE Multi-Function Pin Assignment62
Figure 4.1-27 ML51UC0AE / ML51UB9AE Multi Function Pin Assignment64
Figure 4.1-28 ML51FB9AE Multi Function Pin Assignment66
Figure 4.1-29 ML51OB9AE Multi Function Pin Assignment67
Figure 4.1-30 ML51XB9AE Multi Function Pin Assignment68
Figure 4.1-31 ML51DB9AE Multi Function Pin Assignment70
Figure 4.1-32 ML51BB9AE Pin Assignment71
Pin Description72
ML51/ML54/ML56 Series Pin Mapping72
ML51/ML54/ML56 Series Pin Functional Description74
Block Diagram79
ML51/ML54/ML56 Series Full Function Block79
Figure 5.1-1 Functional Block Diagram79
Functional Description80
Memory Organization80
Program Memory80
Figure 6.1-1 ML51/ML54/ML56 Series Program Memory Map81
Security Protection Memory (SPROM)82
Figure 6.1-2 SPROM Memory Mapping and SPROM Security Mode82
96-Bit Unique Code (UID)83
Data Flash83
Data Memory84
Figure 6.1-3 Data Memory Map84
Figure 6.1-4 Internal 256 Bytes RAM Addressing85
Config Bytes86
Figure 6.1-5 CONFIG0 any Reset Reloading87
Figure 6.1-6 CONFIG2 Power-On Reset Reloading89
Special Function Register (SFR)91
Table 6.1-1Special Function Register (SFR) Memory Map99
Table 6.1-2 SFR Definitions and Reset Values111
System Manager292
Clock System292
Figure 6.2-1 Clock System Block Diagram292
Power Management301
Table 6.2-1 Power Mode Table301
Table 6.2-2 Entry Setting of Power-Down Mode301
Power Monitering and Reset304
Figure 6.2-2 Brown-Out Detection Block Diagram306
Table 6.2-3 BOF Reset Value306
Figure 6.2-3 Boot Selecting Diagram318
Interrupt System321
Table 6.2-4 Interrupt Vectors321
Table 6.2-5 Interrupt Priority Level Setting328
Table 6.2-6 Characteristics of each Interrupt Source330
Flash Memory Control341
In-Application-Programming (IAP)341
Figure 6.3-1 IAP Modes and Command Codes350
Figure 6.3-2. CRC-8 Block Diagram351
In-Circuit-Programming (ICP)357
On-Chip-Debugger (ICE)358
GPIO Port Structure and Operation361
GPIO Mode361
Table 6.4-1 Configuration for Different I/O Modes361
Figure 6.4-1 Quasi-Bidirectional Mode Structure362
Figure 6.4-2 Push-Pull Mode Structure362
Figure 6.4-3 Input-Only Mode Structure363
Figure 6.4-4 Open-Drain Mode Structure363
External Interrupt Pins380
Table 6.4-2 External Interrupt Pin Multi-Function Pin List380
Pin Interrupt (PIT)382
Figure 6.4-5 Pin Interface Block Diagram382
Timer389
Overview389
Timer/Counter 0 and 1389
Figure 6.5-1 Timer/Counters 0 and 1 in Mode 0390
Figure 6.5-2 Timer/Counters 0 and 1 in Mode 1390
Figure 6.5-3 Timer/Counters 0 and 1 in Mode 2391
Figure 6.5-4 Timer/Counter 0 in Mode 3391
Timer 2 and Input Capture401
Figure 6.5-5 Timer 2 Block Diagram401
Figure 6.5-6 Timer 2 Auto-Reload Mode and Input Capture Module Functional Block Diagram402
Figure 6.5-7 Timer 2 Compare Mode and Input Capture Module Functional Block Diagram403
Timer 3410
Figure 6.5-8 Timer 3 Block Diagram410
Watchdog Timer (WDT)414
Time-Out Reset Timer414
Table 6.6-1 Watchdog Timer-Out Interval under Different Pre-Scalars414
General Purpose Timer415
Figure 6.6-1 WDT as a Time-Out Reset Timer415
Figure 6.6-2 Watchdog Timer Block Diagram415
Register Description416
Typical Structure of WDT Service Routine419
Self Wake-Up Timer (WKT)421
Overview421
Block Diagram421
Figure 6.7-1 Self Wake-Up Timer Block Diagram421
Control Register422
Pulse Width Modulated (PWM)428
Overview428
Features428
Block Diagram429
Figure 6.8-1 PWM0 Block Diagram429
Figure 6.8-2 PWM1/ PWM2 / PWM3 Block Diagram430
Functional Description431
Figure 6.8-3 PWM0 and Fault Brake Output Control Block Diagram432
Figure 6.8-4 PWM1/2/3 Control Block Diagram433
Figure 6.8-5 PWM Edge-Aligned Type Waveform444
Figure 6.8-6 PWM Center-Aligned Type Waveform445
Figure 6.8-7 PWM Complementary Mode with Dead-Time Insertion447
Figure 6.8-8 Fault Brake Function Block Diagram453
PWM Interrupt456
Figure 6.8-9 PWM Interrupt Type458
Register Description459
Serial Port (UART0 & UART1)475
Overview475
Features475
Functional Description476
Figure 6.9-1 Serial Port Mode 0 Timing Diagram476
Figure 6.9-2 Serial Port Mode 1 Timing Diagram477
Figure 6.9-3 Serial Port Mode 2 and 3 Timing Diagram478
Table 6.9-1 Serial Port 0 Mode / Baud Rate Description479
Table 6.9-2 Serial Port 1 Mode / Baud Rate Description480
Register Description486
Smart Card Interface (SC)503
Overview503
Features503
Block Diagram503
Figure 6.10-1 SC Controller Block Diagram503
Operating Modes504
Figure 6.10-2 SC Interface Connection504
Table 6.10-1 SC Activation and Cold Reset Sequence505
Table 6.10-2 SC Warm Reset Sequence505
Smart Card Data Transfer506
Figure 6.10-3 SC Data Character506
Table 6.10-3 SC Deactivation Sequence506
Figure 6.10-4 Initial Character TS507
Figure 6.10-5 SC Error Signal507
Figure 6.10-6 Transmit Direction Block Guard Time Operation508
Figure 6.10-7 Receive Direction Block Guard Time Operation508
Figure 6.10-8 Extra Guard Time Operation508
Register Description509
Serial Peripheral Interface (SPI)522
Overview522
Features522
Block Diagram523
Figure 6.11-1 SPI Block Diagram523
Functional Description524
Figure 6.11-2 SPI Multi-Master, Multi-Slave Interconnection524
Figure 6.11-3 SPI Single-Master / Single-Slave Interconnection525
Figure 6.11-4 SPI Clock Formats526
Figure 6.11-5 SPI Clock and Data Format with CPHA = 0527
Figure 6.11-6 SPI Clock and Data Format with CPHA = 1527
Table 6.11-1 Slave Select Pin Configurations528
Figure 6.11-7 SPI Overrun Waveform529
Figure 6.11-8 SPI Interrupt Request529
Register Description530
Inter-Integrated Circuit (I 2 C)536
Overview536
Features536
Functional Description536
Figure 6.12-1 I 2 C Bus Interconnection536
Figure 6.12-2 I C Bus Protocol537
Figure 6.12-3 START, Repeated START, and STOP Conditions537
Figure 6.12-4 Master Transmits Data to Slave by 7-Bit538
Figure 6.12-5 Master Reads Data from Slave by 7-Bit538
Figure 6.12-6 Data Format of One I539
Figure 6.12-7 Acknowledge Bit539
Figure 6.12-8 Arbitration Procedure of Two Masters540
Figure 6.12-9 Control I540
Figure 6.12-10 Flow and Status of Master Transmitter Mode542
Figure 6.12-11 Flow and Status of Master Receiver Mode543
Figure 6.12-12 Flow and Status of Slave Receiver Mode545
Figure 6.12-13 Flow and Status of General Call Mode546
C Time-Out547
Figure 6.12-14 Status Display in I2STAT Register547
Figure 6.12-15 I C Time-Out Counter548
C Interrupt550
Register Description550
Typical Structure of I C Interrupt Service Routine557
12-Bit Analog-To-Digital Converter (ADC)561
Overview561
Block Diagram562
Figure 6.13-1 12-Bit ADC Block Diagram562
Functional Description563
Figure 6.13-2 External Triggering ADC Circuit564
Figure 6.13-3 ADC Result Comparator564
Figure 6.13-4 ADC Continues Mode with DMA565
Register Description566
Voltage Reference583
Ref583
Figure 6.14-1 VREF Block Diagram583
Figure 6.14-2 Pre-Load Timing583
Analog Comparator Controller (ACMP)585
Overview585
Feature585
Block Diagram586
Figure 6.15-1 Analog Comparator Block Diagram586
Functional Description587
Figure 6.15-2 Comparator Hysteresis Function587
Figure 6.15-3 Comparator Reference Voltage Block Diagram588
Figure 6.15-4 Analog Comparator Interrupt Sources588
Register Description589
PDMA Controller (PDMA)595
Overview595
Feature595
Block Diagram595
Figure 6.16-1 PDMA Interface Diagram595
Functional Description596
Figure 6.16-2 PDMA Controller Block Diagram596
Figure 6.16-3 CRC-8 Block Diagram598
Register Description599
LCD Driver610
Overview610
Features610
Block Diagram611
Figure 6.17-1 LCD Block Diagram611
Functional Description612
Figure 6.17-2. LCD Register Map Example613
Figure 6.17-3 One Frame of LCD Energized613
Figure 6.17-4. Example of Type a and Type B 8 COM and SEG Driving Signals of 1/3 Bias614
Figure 6.17-5. Example of Type a and Type B 8 COM and SEG Driving Signals of 1/4 Bias615
Table 6.17-1 VLCD Source Selection Table616
Table 6.17-2 LCD Driving Mode Regiter Setting616
Register Description618
LCD Program Flow633
Real Time Clock (RTC)634
Overview634
Features634
Block Diagram635
Figure 6.18-1 RTC Block Diagram635
Functional Description636
Table 6.18-1 RTC Read/Write Enable637
Table 6.18-212/24 Hour Time Scale Selection638
Table 6.18-3 Registers Value after Powered on639
Register Description640
Table 6.19-1 All Touch Key Pins Select Source List667
Figure 6.19-1Touch Key Block Diagram668
Figure 6.19-2 Touch Key Sensing Method670
Figure 6.19-3 Finger Touch Detection Method671
Figure 6.19-4 Touch Key Controller Interrupt Modes for Threshold Control673
Table 6.20-1 Instruction Set and Addressing Modes696
Table 6.20-2 Instructions Affect Flag Settings697
Table 6.20-3 Instruction Set701
Figure 9.1-1 LQFP 64L Package Dimension705
Figure 9.2-1 LQFP-48 Package Dimension706
Figure 9.3-1 LFP44 Package Dimension707
Figure 9.4-1 QFN-33 Package Dimension708
Figure 9.5-1 LQFP-32 Package Dimension709
Figure 9.6-1 TSSOP-28 Package Dimension710
Figure 9.7-1 SOP-28 Package Dimension711
Figure 9.8-1 TSSOP-20 Package Dimension712
Figure 9.9-1 SOP-20 Package Dimension713
Figure 9.10-1 QFN-20 Package Dimension714
Figure 9.11-1 TSSOP-14 Package Dimension715
Figure 9.12-1 MSOP-10 Package Dimension716
Table 10.1-1 List of Abbreviations717

Brand	Nuvoton
Model	NuMicro Series
Category	Microcontrollers
Language	English

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