NXP Semiconductors MWCT1014SF Series

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MWCT101xS Series Reference

Manual

Supports MWCT1014SFxxx, MWCT1015SFxxx, MWCT1016SFxxx

Document Number: MWCT101XSFRM

Rev. 3, 07/2019

Main Page

Default Chapter3
- Table of Contents3
Chapter 1 About this Manual43
- Audience43
- Organization43
- Module Descriptions43
  - Example: Chip-Specific Information that Clarifies Content in the same Chapter44
  - Example: Chip-Specific Information that Refers to a Different Chapter45
- Register Descriptions46
- Conventions47
Chapter 2 Introduction51
- Overview51
- Mwct101Xs Series Introduction51
- Feature Summary52
- Block Diagram55
- Feature Comparison56
- Applications58
- Module Functional Categories58
Chapter 3 Memory Map65
- Introduction65
- SRAM Memory Map65
- Flash Memory Map65
- Peripheral Bridge (AIPS-Lite) Memory Map66
  - Read-After-Write Sequence and Required Serialization of Memory Operations67
- Private Peripheral Bus (PPB) Memory Map68
- Aliased Bit-Band Regions68
Chapter 4 Signal Multiplexing and Pin Assignment71
- Introduction71
- Functional Description71
- Pad Description72
- Default Pad State73
- Signal Multiplexing Sheet74
  - IO Signal Table74
  - Input Muxing Table76
- Pinout Diagrams77
Chapter 5 Security Overview79
- Introduction79
- Device Security79
- Security Use Case Examples81
- Steps Required before Failure Analysis86
- Security Programming Flow Example (Secure Boot)87
Chapter 6 Safety Overview89
- Introduction89
- Wct101Xs Safety Concept90
Chapter 7 Core Overview97
- Arm Cortex-M4F Core Configuration97
- Nested Vectored Interrupt Controller (NVIC) Configuration100
- Asynchronous Wake-Up Interrupt Controller (AWIC) Configuration102
  - Wake-Up Sources102
- FPU Configuration103
- JTAG Controller Configuration104
Chapter 8 Miscellaneous Control Module (MCM)105
- Chip-Specific MCM Information105
- Introduction105
  - Features105
- Memory Map/Register Descriptions106
- Functional Description129
  - Interrupts129
System Integration Module (SIM)131
- Chip-Specific SIM Information131
  - SIM Register Bitfield Implementation131
- Introduction131
  - Features131
- Memory Map and Register Definition132
  - SIM Register Descriptions132
Chapter 10 Port Control and Interrupts (PORT)159
- Chip-Specific PORT Information159
- Introduction162
- Overview162
  - Features162
  - Modes of Operation163
- External Signal Description164
- Detailed Signal Description164
- Memory Map and Register Definition164
- Functional Description179
Chapter 11 General-Purpose Input/Output (GPIO)183
- Chip-Specific GPIO Information183
- Introduction184
- Memory Map and Register Definition186
  - GPIO Register Descriptions186
- Functional Description193
  - General-Purpose Input193
  - General-Purpose Output193
Chapter 12 Crossbar Switch Lite (AXBS-Lite)195
- Chip-Specific AXBS-Lite Information195
  - Crossbar Switch Master Assignments195
  - Crossbar Switch Slave Assignments195
- Introduction196
  - Features196
- Functional Description196
  - General Operation197
  - Arbitration197
- Initialization/Application Information199
Chapter 13 Memory Protection Unit (MPU)201
- Chip-Specific MPU Information201
- Introduction202
- Overview203
  - Block Diagram203
  - Features204
- MPU Register Descriptions204
- Functional Description231
- Initialization Information234
- Application Information234
Chapter 14 Peripheral Bridge (AIPS-Lite)237
- Chip-Specific AIPS Information237
  - Instantiation Information237
  - Memory Maps237
- Introduction238
  - Features238
  - General Operation238
- Memory Map/Register Definition239
  - AIPS Register Descriptions239
- Functional Description283
  - Access Support283
Chapter 15 Direct Memory Access Multiplexer (DMAMUX)285
- Chip-Specific DMAMUX Information285
  - Number of Channels285
  - DMA Transfers Via TRGMUX Trigger285
- Introduction285
- Memory Map/Register Definition287
  - DMAMUX Register Descriptions287
- Functional Description289
- Initialization/Application Information293
  - Reset293
  - Enabling and Configuring Sources293
Chapter 16 Enhanced Direct Memory Access (Edma)297
- Chip-Specific Edma Information297
  - Number of Channels297
- Introduction297
- Modes of Operation301
- Memory Map/Register Definition301
- Functional Description351
- Initialization/Application Information357
Chapter 17 Trigger MUX Control (TRGMUX)373
- Chip-Specific TRGMUX Information373
  - Module Interconnectivity373
  - Chip-Specific TRGMUX Registers377
- Introduction377
- Features377
- Memory Map and Register Definition378
  - TRGMUX Register Descriptions378
Chapter 18 External Watchdog Monitor (EWM)417
- Chip-Specific EWM Information417
- Introduction418
- EWM Signal Descriptions420
- Memory Map/Register Definition421
  - EWM Register Descriptions421
- Functional Description426
Chapter 19 Error Injection Module (EIM)431
- Chip-Specific EIM Information431
  - EIM Channel Assignments431
- Introduction431
  - Overview432
  - Features433
- EIM Register Descriptions433
- Functional Description441
  - Error Injection Scenarios441
Chapter 20 Error Reporting Module (ERM)443
- Chip-Specific ERM Information443
  - Sources of Memory Error Events443
- Introduction443
  - Overview443
  - Features444
- ERM Register Descriptions444
- Functional Description450
  - Single-Bit Correction Events450
  - Non-Correctable Error Events451
- Initialization452
Chapter 21 Watchdog Timer (WDOG)453
- Chip-Specific WDOG Information453
- Introduction455
  - Features455
  - Block Diagram456
- Memory Map and Register Definition456
  - WDOG Register Descriptions456
- Functional Description463
- Application Information470
Chapter 22 Cyclic Redundancy Check (CRC)473
- Chip-Specific CRC Information473
- Introduction473
- Memory Map and Register Descriptions474
  - CRC Register Descriptions474
- Functional Description479
Chapter 23 Reset and Boot483
- Introduction483
- Reset483
- Boot490
Chapter 24 Reset Control Module (RCM)493
- Chip-Specific RCM Information493
- Reset Pin Filter Operation in STOP1/2 Modes493
- Introduction493
- Reset Memory Map and Register Descriptions494
Chapter 25 Clock Distribution509
- Introduction509
- High Level Clocking Diagram509
- Clock Definitions510
- Internal Clocking Requirements512
- Clock Gating517
- Module Clocks517
Chapter 26 System Clock Generator (SCG)529
- Chip-Specific SCG Information529
- Introduction531
  - Features531
- Memory Map/Register Definition532
Chapter 27 Chip-Specific PCC Information565
- Features566
- Functional Description567
- PCC FTFC Register (PCC_FTFC)569
- PCC DMAMUX Register (PCC_DMAMUX)570
- PCC Flexcan0 Register (Pcc_Flexcan0)572
- PCC Flexcan1 Register (Pcc_Flexcan1)573
- PCC FTM3 Register (PCC_FTM3)575
- PCC ADC1 Register (PCC_ADC1)576
- PCC Flexcan2 Register (Pcc_Flexcan2)578
- PCC LPSPI0 Register (PCC_LPSPI0)579
- PCC LPSPI1 Register (PCC_LPSPI1)581
- PCC LPSPI2 Register (PCC_LPSPI2)582
- PCC PDB1 Register (PCC_PDB1)584
- PCC CRC Register (PCC_CRC)586
- PCC PDB0 Register (PCC_PDB0)587
- PCC LPIT Register (PCC_LPIT)589
- PCC FTM0 Register (PCC_FTM0)590
- PCC FTM1 Register (PCC_FTM1)592
- PCC FTM2 Register (PCC_FTM2)593
- PCC ADC0 Register (PCC_ADC0)595
- PCC RTC Register (PCC_RTC)597
- PCC LPTMR0 Register (PCC_LPTMR0)598
- PCC PORTA Register (PCC_PORTA)600
- PCC PORTB Register (PCC_PORTB)602
- PCC PORTC Register (PCC_PORTC)603
- PCC PORTD Register (PCC_PORTD)605
- PCC PORTE Register (PCC_PORTE)606
- PCC Flexio Register (Pcc_Flexio)608
- PCC EWM Register (PCC_EWM)609
- PCC LPI2C0 Register (PCC_LPI2C0)611
- PCC LPI2C1 Register (PCC_LPI2C1)612
- PCC LPUART0 Register (PCC_LPUART0)614
- PCC LPUART1 Register (PCC_LPUART1)615
- PCC LPUART2 Register (PCC_LPUART2)617
- PCC FTM4 Register (PCC_FTM4)619
- PCC FTM5 Register (PCC_FTM5)620
- PCC FTM6 Register (PCC_FTM6)622
- PCC FTM7 Register (PCC_FTM7)624
- PCC CMP0 Register (PCC_CMP0)625
- PCC QSPI Register (PCC_QSPI)627
Chapter 28 Memories and Memory Interfaces629
- Introduction629
- Flash Memory Controller and Flash Memory Modules629
- SRAM Configuration629
Chapter 29 Chip-Specific LMEM Information635
- Block Diagram636
- Cache Features637
- Functional Description648
- SRAM Function649
- Cache Function651
- Cache Control652
Chapter 30657
- Chip-Specific MSCM Information657
- Overview658
- MSCM Memory Map/Register Definition659
Chapter 31691
- Chip-Specific FMC Information691
- Chip-Specific FTFC Information697
Chapter 32698
- Flash Memory Types698
- Flash Memory Map708
- Flash Memory Security709
- Simultaneous Operations on PFLASH Read Partitions710
- Program Flash 0 IFR Map717
  - Register Descriptions718
  - Functional Description736
- Flexnvm Description738
- Interrupts741
- Flash Operation in Low-Power Modes742
- Read While Write (RWW)743
- FTFC Command Operations744
- Margin Read Commands750
- Flash Command Descriptions751
- Security777
- Cryptographic Services Engine (Csec)779
- Reset Sequence817
Chapter 33 Chip-Specific Quadspi Information819
- Use Case820
- External Memory Options821
- Recommended Programming Sequence822
- Quadspi_Soccr[Soccfg] Implementation823
- Introduction825
- Flash Memory Mapped AMBA Bus879
- Interrupt Signals884
- Functional Description885
- Byte Ordering - Endianness912
  - Programming Flash Data913
  - Reading Flash Data into the AHB Buffer914
- Driving Flash Control Signals in Single and Dual Mode915
- Sampling of Serial Flash Input Data921
  - Supported Read Modes922
  - Data Strobe (DQS) Sampling Method925
- Data Input Hold Requirement of Flash928
- Introduction929
Chapter 34930
- Entering and Exiting Power Modes930
- Clocking Modes931
- Shutdown Sequencing for Power Modes936
- Quadspi Operation940
  - Introduction941
  - Memory Map and Register Descriptions943
Chapter 35944
- SMC Parameter Register (SMC_PARAM)944
- Power Mode Protection Register (SMC_PMPROT)945
- Power Mode Control Register (SMC_PMCTRL)947
- Stop Control Register (SMC_STOPCTRL)949
- Power Mode Status Register (SMC_PMSTAT)950
- Functional Description951
- Power Mode Entry/Exit Sequencing952
- Run Modes955
- Stop Modes957
- Debug in Low Power Modes958
Chapter 36 Chip-Specific PMC Information961
- Modes of Operation962
- Low Voltage Reset (LVR) Operation963
- PMC Register Descriptions964
- Instantiation Information971
Chapter 37 ADC Connections/Channel Assignment972
- DMA Support on ADC973
- ADC Internal Supply Monitoring974
- ADC Trigger Sources975
  - PDB Triggering Scheme977
  - TRGMUX Trigger Scheme978
- Trigger Latching and Arbitration979
- ADC Triggering Configurations981
- ADC Low-Power Modes988
- ADC Calibration Scheme990
Chapter 38993
- Chip-Specific ADC Information993
- Block Diagram994
- ADC Signal Descriptions995
- Chip-Specific CMP Information1047
Chapter 391048
- CMP External References1048
- CMP Trigger Mode1049
  - Introduction1050
  - Features1051
- Bit DAC Key Features1052
- CMP Block Diagram1053
- CMP Pin Descriptions1055
- CMP Functional Modes1056
  - Disabled Mode (# 1)1057
  - Windowed/Filtered Mode (#7)1065
- Memory Map/Register Definitions1066
  - CMP Control Register 1 (Cmpx_C1)1070
  - CMP Control Register 2 (Cmpx_C2)1073
- CMP Functional Description1075
  - Low-Pass Filter1076
  - Interrupts1078
- DAC Functional Description1079
  - DAC Clocks1080
- Chip-Specific PDB Information1083
Chapter 401084
- PDB Trigger Interconnections with ADC and TRGMUX1084
- Pulse-Out Enable Register Implementation1091
- Implementation1092
  - Block Diagram1093
  - Modes of Operation1094
- Status and Control Register (Pdbx_Sc)1098
- Modulus Register (Pdbx_Mod)1101
- Interrupt Delay Register (Pdbx_Idly)1102
- Channel N Status Register (Pdbx_Chns)1103
- Channel N Delay 0 Register (Pdbx_Chndly0)1104
- Channel N Delay 1 Register (Pdbx_Chndly1)1105
- Channel N Delay 3 Register (Pdbx_Chndly3)1106
- Channel N Delay 4 Register (Pdbx_Chndly4)1107
- Channel N Delay 6 Register (Pdbx_Chndly6)1108
- Channel N Delay 7 Register (Pdbx_Chndly7)1109
- Pulse-Out N Delay Register (Pdbx_Pondly)1110
- PDB Trigger Input Source Selection1113
- Updating the Delay Registers1114
- Interrupts1116
- Impact of Using the Prescaler and Multiplication Factor on Timing Resolution1117
Chapter 41 Chip-Specific FTM Information1119
- FTM Interrupts1120
  - FTM Hardware Triggers and Synchronization1121
  - FTM Input Capture Options1124
  - FTM Modulation Implementation1125
  - FTM Global Time Base1126
    - Introduction1127
    - Modes of Operation1129
- FTM Signal Descriptions1131
  - Register Descriptions1132
  - Functional Description1189
- Prescaler1190
- Channel Modes1196
- Input Capture Mode1198
- Output Compare Mode1203
- Edge-Aligned PWM (EPWM) Mode1204
- Center-Aligned PWM (CPWM) Mode1206
- Combine Mode1208
- Modified Combine PWM Mode1216
- Complementary Mode1220
- Registers Updated from Write Buffers1221
- PWM Synchronization1223
- Inverting1238
- Software Output Control Mode1239
- Deadtime Insertion1241
- Output Mask1245
- Fault Control1246
- Polarity Control1250
- Initialization1251
- External Trigger1252
- Initialization Trigger1253
- Capture Test Mode1256
- Dual Edge Capture Mode1257
  - Quadrature Decoder Mode1265
  - Debug Mode1271
  - Reload Points1272
  - Global Load1275
  - Global Time Base (GTB)1276
  - Channel Trigger Output1277
  - External Control of Channels Output1278
- Reset Overview1289
  - FTM Interrupts1291
  - Initialization Procedure1292
- Chip-Specific LPIT Information1295
Chapter 421296
- LPIT Input Triggers1296
- Timer Modes1320
- Channel Chaining1321
- Detailed Timing1322
Chapter 431335
- Chip-Specific LPTMR Information1335
- Introduction1336
- LPTMR Signal Descriptions1337
Chapter 441349
- Chip-Specific RTC Information1349
Chapter 451367
- Chip-Specific LPSPI Information1367
Chapter 46 Chip-Specific LPI2C Information1409
- Introduction1410
- Features1411
- Block Diagram1413
- Signal Descriptions1414
- Memory Map and Registers1415
- LPI2C Register Descriptions1416
- Functional Description1454
- Clocking and Resets1455
- Slave Mode1461
- Interrupts and DMA Requests1463
- Peripheral Triggers1466
Chapter 471467
- Chip-Specific LPUART Information1467
  - Introduction1468
  - Modes of Operation1469
- Register Definition1471
Chapter 481515
- Chip-Specific Flexio Information1515
  - Features1516
  - Modes of Operation1517
- Memory Map and Registers1518
- Chip-Specific Flexcan Information1563
Chapter 491564
- Flexcan External Time Tick1564
- Flexcan Oscillator Clock1565
- Flexcan Signal Descriptions1572
- CM4 ROM Table1715
- Debug Port1716
- Debug Port Pin Descriptions1717
- MDM-AP Status and Control Registers1718
- Ahb-Ap1722
- Core Trace Connectivity1723
- Debug in Low-Power Modes1724
  - Debug Module State in Low-Power Modes1725
Chapter 511727
- Chip-Specific JTAGC Information1727
- Features1728
- External Signal Description1730
- Test Mode Select (TMS)1731
- Device Identification Register1732
- Boundary Scan Register1733
- TAP Controller State Machine1734
- JTAGC Block Instructions1736
- Boundary Scan1739

Brand	NXP Semiconductors
Model	MWCT1014SF Series
Category	Semiconductors
Language	English

NXP Semiconductors MWCT1014SF Series - User Manual

Table of Contents

NXP Semiconductors MWCT1014SF Series Specifications