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S32K1xx Series Reference Manual
Supports S32K116, S32K118, S32K142, S32K144, S32K146, and
S32K148
Document Number: S32K1XXRM
Rev. 4, 06/2017
Preliminary
2
Table of Contents
Main Page
S32K1xx Reference Manual (Supports S32K116, S32K118, S32K142, S32K144, S32K146, and S32K148)
1
Contents
3
Chapter 1​: About This Manual
47
Audience
47
Organization
47
Module descriptions
47
Example: chip-specific information that clarifies content in the same chapter
48
Example: chip-specific information that refers to a different chapter
49
Register descriptions
50
Conventions
51
Notes, Cautions, and Warnings
51
Numbering systems
51
Typographic notation
52
Special terms
52
Chapter 2​: Introduction
55
Overview
55
S32K1xx Series introduction
55
S32K14x
55
S32K11x
56
Feature summary
57
Block diagram
60
Feature comparison
62
Applications
63
Module functional categories
64
ARM Cortex-M4F Core Modules
66
ARM Cortex-M0+ Core Modules
66
System modules
67
Memories and memory interfaces
68
Power Management
68
Clocking
69
Analog modules
69
Timer modules
70
Communication interfaces
70
Debug modules
71
Chapter 3​: Memory Map
73
Introduction
73
SRAM memory map
73
Flash memory map
74
Peripheral bridge (AIPS-Lite) memory map
74
Read-after-write sequence and required serialization of memory operations
75
Private Peripheral Bus (PPB) memory map
76
Aliased bit-band regions for CM4 core
77
Chapter 4​: Signal Multiplexing and Pin Assignment
79
Introduction
79
Functional description
79
Pad description
80
Default pad state
81
Signal Multiplexing sheet
82
IO Signal Table
82
Input muxing table
83
Pinout diagrams
84
Chapter 5​: Security Overview
85
Introduction
85
Device security
85
Flash memory security
85
Flash memory security interactions with debug
86
Cryptographic Services Engine (CSEc) security features
86
Device Boot modes
87
Security use case examples
87
Secure boot: check bootloader for integrity and authenticity
87
Chain of trust: check flash memory for integrity and authenticity
88
Secure communication
89
Component protection
90
Message-authentication example
91
Steps required before failure analysis
92
Security programming flow example (Secure Boot)
93
Chapter 6​: Safety Overview
95
Introduction
95
S32K1xx safety concept
96
Cortex-M4/M0+ Structural Core Self Test (SCST)
97
ECC on RAM and flash memory
98
Power supply monitoring
98
Clock monitoring
99
Temporal protection
99
Operational interference protection
99
System Memory Protection Unit (MPU)
100
Peripheral protection
100
Register protection
100
CRC
101
Diversity of system resources
101
Chapters 7-22 Core and System Modules
103
Chapter 7​: Core Overview
103
ARM Cortex-M4F core configuration
103
Buses, interconnects, and interfaces
104
System Tick Timer
104
Debug facilities
104
Caches
105
Core privilege levels
105
Nested Vectored Interrupt Controller (NVIC) Configuration
106
Interrupt priority levels
106
Non-maskable interrupt
106
Determining the bitfield and register location for configuring a particular interrupt
107
Asynchronous Wake-up Interrupt Controller (AWIC) Configuration
108
Wake-up sources
108
FPU configuration
109
JTAG controller configuration
110
Chapter 8​: Miscellaneous Control Module (MCM)
111
Chip-specific MCM information
111
Introduction
111
Features
111
Memory map/register descriptions
112
MCM
112
MCM_PLASC
113
MCM_PLAMC
113
MCM_CPCR
115
MCM_ISCR
118
MCM_PID
121
MCM_CPO
122
MCM_LMDRn
123
MCM_LMDR2
126
MCM_LMPECR
130
MCM_LMPEIR
130
MCM_LMFAR
132
MCM_LMFATR
133
MCM_LMFDHR
134
MCM_LMFDLR
134
Functional description
135
Interrupts
135
Chapter 9​: System Integration Module (SIM)
137
Chip-specific SIM information
137
SIM register bitfield implementation
137
Introduction
137
Features
137
Memory map and register definition
138
SIM register descriptions
138
SIM Memory map
138
Chip Control register (CHIP​CTL)
139
FTM Option Register 0 (FTMO​PT0)
142
LPO Clock Select Register (LPOC​LKS)
145
ADC Options Register (ADCO​PT)
147
FTM Option Register 1 (FTMO​PT1)
148
Miscellaneous control register 0 (MISC​TRL0)
150
System Device Identification Register (SDID)
153
Platform Clock Gating Control Register (PLAT​CGC)
155
Flash Configuration Register 1 (FCFG​1)
156
Unique Identification Register High (UIDH)
158
Unique Identification Register Mid-High (UIDM​H)
159
Unique Identification Register Mid Low (UIDM​L)
160
Unique Identification Register Low (UIDL)
161
System Clock Divider Register 4 (CLKD​IV4)
162
Miscellaneous Control register 1 (MISC​TRL1)
163
Chapter 10​: Port Control and Interrupts (PORT)
165
Chip-specific PORT information
165
Number of PCRs
165
I/O configuration sequence
166
Digital input filter configuration sequence
166
Digital input filter configuration sequence while using GPIO interrupt
166
Digital input filter configuration sequence while using NMI
167
Introduction
167
Overview
167
Features
168
Modes of operation
168
Run mode
168
Wait mode
168
Stop mode
169
Debug mode
169
External signal description
169
Detailed signal description
169
Memory map and register definition
170
PORT
170
PORT_PCRn
172
PORT_GPCLR
175
PORT_GPCHR
175
PORT_GICLR
176
PORT_GICHR
176
PORT_ISFR
177
PORT_DFER
178
PORT_DFCR
178
PORT_DFWR
179
Functional description
179
Pin control
179
Global pin control
180
Global interrupt control
181
External interrupts
181
Digital filter
182
Chapter 11​: General-Purpose Input/Output (GPIO)
183
Chip-specific GPIO information
183
Instantiation information
183
GPIO ports memory map
183
Introduction
184
Features
184
Modes of operation
184
GPIO signal descriptions
185
Detailed signal description
185
Memory map and register definition
186
GPIO register descriptions
186
GPIO Memory map
186
Port Data Output Register (PDOR)
187
Port Set Output Register (PSOR)
188
Port Clear Output Register (PCOR)
189
Port Toggle Output Register (PTOR)
189
Port Data Input Register (PDIR)
190
Port Data Direction Register (PDDR)
191
Port Input Disable Register (PIDR)
192
Functional description
193
General-purpose input
193
General-purpose output
193
Chapter 12​: Crossbar Switch Lite (AXBS-Lite)
195
Chip-specific AXBS-Lite information
195
Crossbar Switch master assignments
195
Crossbar Switch slave assignments
195
Introduction
196
Features
196
Functional Description
197
General operation
197
Arbitration
197
Arbitration during undefined length bursts
198
Fixed-priority operation
198
Round-robin priority operation
199
Initialization/application information
199
Chapter 13​: Memory Protection Unit (MPU)
201
Chip-specific MPU information
201
MPU Slave Port Assignments
201
MPU Logical Bus Master Assignments
202
Current PID
202
Region descriptors and slave port configuration
202
Introduction
202
Overview
203
Block diagram
203
Features
204
MPU register descriptions
204
MPU Memory map
205
Control/Error Status Register (CESR)
207
Error Address Register, slave port n (EAR0 - EAR4)
210
Error Detail Register, slave port n (EDR0 - EDR4)
211
Region Descriptor n, Word 0 (RGD0​_​WOR​D0 - RGD1​5_​WO​RD0)
212
Region Descriptor 0, Word 1 (RGD0​_​WOR​D1)
214
Region Descriptor 0, Word 2 (RGD0​_​WOR​D2)
215
Region Descriptor 0, Word 3 (RGD0​_​WOR​D3)
218
Region Descriptor n, Word 1 (RGD1​_​WOR​D1 - RGD1​5_​WO​RD1)
219
Region Descriptor n, Word 2 (RGD1​_​WOR​D2 - RGD1​5_​WO​RD2)
220
Region Descriptor n, Word 3 (RGD1​_​WOR​D3 - RGD1​5_​WO​RD3)
223
Region Descriptor Alternate Access Control 0 (RGDA​AC0)
225
Region Descriptor Alternate Access Control n (RGDA​AC1 - RGDA​AC15)
228
Functional description
231
Access evaluation macro
231
Hit determination
232
Privilege violation determination
232
Putting it all together and error terminations
233
Power management
233
Initialization information
234
Application information
234
Chapter 14​: Peripheral Bridge (AIPS-Lite)
237
Chip-specific AIPS information
237
Instantiation information
237
Memory maps
237
Introduction
238
Features
238
General operation
238
Memory map/register definition
239
AIPS register descriptions
239
AIPS Memory map
239
Master Privilege Register A (MPRA)
239
Peripheral Access Control Register (PACR​A)
242
Peripheral Access Control Register (PACR​B)
244
Peripheral Access Control Register (PACR​D)
246
Off-Platform Peripheral Access Control Register (OPAC​RA)
249
Off-Platform Peripheral Access Control Register (OPAC​RB)
252
Off-Platform Peripheral Access Control Register (OPAC​RC)
255
Off-Platform Peripheral Access Control Register (OPAC​RD)
258
Off-Platform Peripheral Access Control Register (OPAC​RE)
261
Off-Platform Peripheral Access Control Register (OPAC​RF)
263
Off-Platform Peripheral Access Control Register (OPAC​RG)
266
Off-Platform Peripheral Access Control Register (OPAC​RH)
269
Off-Platform Peripheral Access Control Register (OPAC​RI)
270
Off-Platform Peripheral Access Control Register (OPAC​RJ)
274
Off-Platform Peripheral Access Control Register (OPAC​RK)
277
Off-Platform Peripheral Access Control Register (OPAC​RL)
280
Functional description
283
Access support
283
Chapter 15​: Direct Memory Access Multiplexer (DMAMUX)
285
Chip-specific DMAMUX information
285
Number of channels
285
DMA transfers via TRGMUX trigger
285
Introduction
286
Overview
286
Features
286
Modes of operation
287
External signal description
287
Memory map/register definition
287
DMAMUX register descriptions
287
DMAMUX Memory map
288
Channel Configuration register (CHCF​G0 - CHCF​G15)
288
Functional description
289
DMA channels with periodic triggering capability
290
DMA channels with no triggering capability
292
Always-enabled DMA sources
292
Initialization/application information
293
Reset
293
Enabling and configuring sources
293
Chapter 16​: Enhanced Direct Memory Access (eDMA)
297
Chip-specific eDMA information
297
Number of channels
297
Introduction
297
eDMA system block diagram
298
Block parts
298
Features
299
Modes of operation
301
Memory map/register definition
301
TCD memory
301
TCD initialization
301
TCD structure
302
Reserved memory and bit fields
302
DMA register descriptions
302
DMA Memory map
302
Control Register (CR)
314
Error Status Register (ES)
317
Enable Request Register (ERQ)
319
Enable Error Interrupt Register (EEI)
321
Clear Enable Error Interrupt Register (CEEI)
323
Set Enable Error Interrupt Register (SEEI)
324
Clear Enable Request Register (CERQ)
325
Set Enable Request Register (SERQ)
326
Clear DONE Status Bit Register (CDNE)
327
Set START Bit Register (SSRT)
328
Clear Error Register (CERR)
330
Clear Interrupt Request Register (CINT)
331
Interrupt Request Register (INT)
332
Error Register (ERR)
334
Hardware Request Status Register (HRS)
336
Enable Asynchronous Request in Stop Register (EARS)
339
Channel n Priority Register (DCHP​RI3 - DCHP​RI12)
341
TCD Source Address (TCD0​_​SAD​DR - TCD1​5_​SA​DDR)
343
TCD Signed Source Address Offset (TCD0​_​SOF​F - TCD1​5_​SO​FF)
344
TCD Transfer Attributes (TCD0​_​ATT​R - TCD1​5_​AT​TR)
344
TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) (TCD0​_​NBY​TES_​​MLOF​FNO - TCD1​5_​NB​YTES​_​MLO​FFNO)
345
TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) (TCD0​_​NBY​TES_​​MLOF​FYES - TCD1​5_​NB​YTES​_​MLO​FFYE​S)
347
TCD Minor Byte Count (Minor Loop Mapping Disabled) (TCD0​_​NBY​TES_​​MLNO - TCD1​5_​NB​YTES​_​MLN​O)
348
TCD Last Source Address Adjustment (TCD0​_​SLA​ST - TCD1​5_​SL​AST)
350
TCD Destination Address (TCD0​_​DAD​DR - TCD1​5_​DA​DDR)
350
TCD Signed Destination Address Offset (TCD0​_​DOF​F - TCD1​5_​DO​FF)
351
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) (TCD0​_​CIT​ER_​E​LINK​NO - TCD1​5_​CI​TER_​​ELIN​KNO)
352
TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) (TCD0​_​CIT​ER_​E​LINK​YES - TCD1​5_​CI​TER_​​ELIN​KYES)
353
TCD Last Destination Address Adjustment/Scatter Gather Address (TCD0​_​DLA​STSG​A - TCD1​5_​DL​ASTS​GA)
355
TCD Control and Status (TCD0​_​CSR - TCD1​5_​CS​R)
356
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) (TCD0​_​BIT​ER_​E​LINK​YES - TCD1​5_​BI​TER_​​ELIN​KYES)
358
TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) (TCD0​_​BIT​ER_​E​LINK​NO - TCD1​5_​BI​TER_​​ELIN​KNO)
359
Functional description
360
eDMA basic data flow
360
Fault reporting and handling
363
Channel preemption
366
Initialization/application information
366
eDMA initialization
366
Programming errors
368
Arbitration mode considerations
369
Fixed channel arbitration
369
Round-robin channel arbitration
369
Performing DMA transfers
369
Single request
369
Multiple requests
371
Using the modulo feature
373
Monitoring transfer descriptor status
373
Testing for minor loop completion
373
Reading the transfer descriptors of active channels
374
Checking channel preemption status
375
Channel Linking
375
Dynamic programming
376
Dynamically changing the channel priority
376
Dynamic channel linking
377
Dynamic scatter/gather
377
Method 1 (channel not using major loop channel linking)
378
Method 2 (channel using major loop channel linking)
379
Suspend/resume a DMA channel with active hardware service requests
380
Suspend an active DMA channel
380
Resume a DMA channel
380
Chapter 17​: Trigger MUX Control (TRGMUX)
383
Chip-specific TRGMUX information
383
Module interconnectivity
383
Chip-specific TRGMUX registers
387
Introduction
387
Features
387
Memory map and register definition
388
TRGMUX register descriptions
388
TRGMUX Memory map
388
TRGMUX DMAMUX0 Register (DMAM​UX0)
393
TRGMUX EXTOUT0 Register (EXTO​UT0)
394
TRGMUX EXTOUT1 Register (EXTO​UT1)
395
TRGMUX ADC0 Register (ADC0)
397
TRGMUX ADC1 Register (ADC1)
398
TRGMUX CMP0 Register (CMP0)
399
TRGMUX FTM0 Register (FTM0)
401
TRGMUX FTM1 Register (FTM1)
402
TRGMUX FTM2 Register (FTM2)
403
TRGMUX FTM3 Register (FTM3)
405
TRGMUX PDB0 Register (PDB0)
406
TRGMUX PDB1 Register (PDB1)
407
TRGMUX FLEXIO Register (FLEX​IO)
409
TRGMUX LPIT0 Register (LPIT​0)
410
TRGMUX LPUART0 Register (LPUA​RT0)
411
TRGMUX LPUART1 Register (LPUA​RT1)
413
TRGMUX LPI2C0 Register (LPI2​C0)
414
TRGMUX LPSPI0 Register (LPSP​I0)
415
TRGMUX LPSPI1 Register (LPSP​I1)
417
TRGMUX LPTMR0 Register (LPTM​R0)
418
TRGMUX LPI2C1 Register (LPI2​C1)
419
TRGMUX FTM4 Register (FTM4)
421
TRGMUX FTM5 Register (FTM5)
422
TRGMUX FTM6 Register (FTM6)
423
TRGMUX FTM7 Register (FTM7)
425
Chapter 18​: External Watchdog Monitor (EWM)
427
Chip-specific EWM information
427
EWM_OUT signal configuration
427
EWM Memory Map access
427
EWM low-power modes
427
Introduction
427
Features
428
Modes of Operation
428
Stop Mode
429
Debug Mode
429
Block Diagram
429
EWM Signal Descriptions
430
Memory Map/Register Definition
431
EWM register descriptions
431
EWM Memory map
431
Control Register (CTRL)
431
Service Register (SERV)
432
Compare Low Register (CMPL)
433
Compare High Register (CMPH)
434
Clock Prescaler Register (CLKP​RESC​ALER)
435
Functional Description
436
The EWM_OUT_b Signal
436
EWM_OUT_b pin state in low power modes
437
The EWM_in Signal
437
EWM Counter
438
EWM Compare Registers
438
EWM Refresh Mechanism
438
EWM Interrupt
439
Counter clock prescaler
439
Chapter 19​: Error Injection Module (EIM)
441
Chip-specific EIM information
441
EIM channel assignments
441
Introduction
441
Overview
441
Features
442
EIM register descriptions
443
EIM Memory map
444
Error Injection Module Configuration Register (EIMC​R)
444
Error Injection Channel Enable register (EICH​EN)
445
Error Injection Channel Descriptor n, Word0 (EICH​D0_​W​ORD0 - EICH​D1_​W​ORD0)
448
Error Injection Channel Descriptor n, Word1 (EICH​D0_​W​ORD1 - EICH​D1_​W​ORD1)
450
Functional description
451
Chapter 20​: Error Reporting Module (ERM)
453
Chip-specific ERM information
453
Sources of memory error events
453
Introduction
453
Overview
453
Features
454
ERM register descriptions
454
ERM Memory map
454
ERM Configuration Register 0 (CR0)
455
ERM Status Register 0 (SR0)
457
ERM Memory n Error Address Register (EAR0 - EAR1)
459
Functional description
460
Single-bit correction events
460
Non-correctable error events
461
Initialization
462
Chapter 21​: Watchdog timer (WDOG)
463
Chip-specific WDOG information
463
WDOG clocks
463
WDOG low-power modes
463
Default watchdog timeout
463
Introduction
464
Features
464
Block diagram
465
Memory map and register definition
465
WDOG register descriptions
465
WDOG Memory map
465
Watchdog Control and Status Register (CS)
466
Watchdog Counter Register (CNT)
468
Watchdog Timeout Value Register (TOVA​L)
469
Watchdog Window Register (WIN)
471
Functional description
472
Clock source
472
Watchdog refresh mechanism
473
Window mode
474
Refreshing the Watchdog
474
Using interrupts to delay resets
476
Backup reset
476
Functionality in debug and low-power modes
477
Fast testing of the watchdog
477
Testing each byte of the counter
478
Entering user mode
478
Application Information
479
Chapter 22​: Cyclic Redundancy Check (CRC)
481
Chip-specific CRC information
481
Introduction
481
Features
481
Block diagram
482
Modes of operation
482
Run mode
482
Low-power modes (Stop)
482
Memory map and register descriptions
482
CRC register descriptions
482
CRC Memory map
483
CRC Data register (DATA)
483
CRC Polynomial register (GPOL​Y)
484
CRC Control register (CTRL)
485
Functional description
487
CRC initialization/reinitialization
487
CRC calculations
487
16-bit CRC
487
32-bit CRC
488
Transpose feature
488
Types of transpose
489
CRC result complement
490
Chapters 23-24 Reset and Boot
491
Chapter 23​: Reset and Boot
491
Introduction
491
Reset
491
Power-on reset (POR)
492
System reset sources
492
External pin reset
492
RESET_B pin filter
493
Low voltage detect (LVD)
493
Watchdog reset
494
Loss-of-clock (LOC) reset
494
Loss-of-lock (LOL) reset
494
Stop mode acknowledge error (SACKERR)
495
Software reset (SW)
495
Lockup reset (LOCKUP)
495
MDM-AP system reset request
495
MCU Resets
495
Reset pin
496
Debug resets
497
JTAG reset
497
Resetting the debug subsystem
497
Boot
498
Boot sources
498
FOPT boot options
498
Boot sequence
499
Chapter 24​: Reset Control Module (RCM)
501
Chip-specific RCM information
501
Reset pin filter operation in STOP1/2 modes
501
Introduction
501
Reset memory map and register descriptions
502
RCM
502
RCM_VERID
502
RCM_PARAM
503
RCM_SRS
505
RCM_RPC
508
RCM_SSRS
510
RCM_SRIE
512
Chapters 25-28 Clocking
515
Chapter 25​: Clock Distribution
515
Introduction
515
High level clocking diagram
515
Clock definitions
516
Internal clocking requirements
518
Clock divider values after reset
521
HSRUN mode clocking
521
VLPR mode clocking
521
VLPR/VLPS mode entry
522
Clock Gating
522
Module clocks
522
Chapter 26​: System Clock Generator (SCG)
535
Chip-specific SCG information
535
Introduction
537
Features
537
Memory Map/Register Definition
538
SCG
538
SCG_VERID
539
SCG_PARAM
540
SCG_CSR
540
SCG_RCCR
543
SCG_VCCR
545
SCG_HCCR
547
SCG_CLKOUTCNFG
549
SCG_SOSCCSR
551
SCG_SOSCDIV
553
SCG_SOSCCFG
554
SCG_SIRCCSR
556
SCG_SIRCDIV
557
SCG_SIRCCFG
558
SCG_FIRCCSR
559
SCG_FIRCDIV
561
SCG_FIRCCFG
562
SCG_SPLLCSR
563
SCG_SPLLDIV
565
SCG_SPLLCFG
566
Functional description
567
SCG Clock Mode Transitions
567
Chapter 27​: Peripheral Clock Controller (PCC)
571
Chip-specific PCC information
571
Chip-specific PCC register information
571
Introduction
571
Features
571
Functional description
572
Memory map and register definition
573
PCC register descriptions
573
PCC Memory map
573
PCC FTFC Register (PCC_​​FTFC)
574
PCC DMAMUX Register (PCC_​​DMAM​UX)
576
PCC FlexCAN0 Register (PCC_​​Flex​CAN0)
577
PCC FlexCAN1 Register (PCC_​​Flex​CAN1)
579
PCC FTM3 Register (PCC_​​FTM3)
580
PCC ADC1 Register (PCC_​​ADC1)
582
PCC FlexCAN2 Register (PCC_​​Flex​CAN2)
583
PCC LPSPI0 Register (PCC_​​LPSP​I0)
585
PCC LPSPI1 Register (PCC_​​LPSP​I1)
586
PCC LPSPI2 Register (PCC_​​LPSP​I2)
588
PCC PDB1 Register (PCC_​​PDB1)
589
PCC CRC Register (PCC_​​CRC)
591
PCC PDB0 Register (PCC_​​PDB0)
592
PCC LPIT Register (PCC_​​LPIT)
594
PCC FTM0 Register (PCC_​​FTM0)
595
PCC FTM1 Register (PCC_​​FTM1)
597
PCC FTM2 Register (PCC_​​FTM2)
598
PCC ADC0 Register (PCC_​​ADC0)
600
PCC RTC Register (PCC_​​RTC)
602
PCC LPTMR0 Register (PCC_​​LPTM​R0)
603
PCC PORTA Register (PCC_​​PORT​A)
605
PCC PORTB Register (PCC_​​PORT​B)
607
PCC PORTC Register (PCC_​​PORT​C)
608
PCC PORTD Register (PCC_​​PORT​D)
610
PCC PORTE Register (PCC_​​PORT​E)
611
PCC SAI0 Register (PCC_​​SAI0)
613
PCC SAI1 Register (PCC_​​SAI1)
614
PCC FlexIO Register (PCC_​​Flex​IO)
616
PCC EWM Register (PCC_​​EWM)
617
PCC LPI2C0 Register (PCC_​​LPI2​C0)
619
PCC LPI2C1 Register (PCC_​​LPI2​C1)
620
PCC LPUART0 Register (PCC_​​LPUA​RT0)
622
PCC LPUART1 Register (PCC_​​LPUA​RT1)
623
PCC LPUART2 Register (PCC_​​LPUA​RT2)
625
PCC FTM4 Register (PCC_​​FTM4)
627
PCC FTM5 Register (PCC_​​FTM5)
628
PCC FTM6 Register (PCC_​​FTM6)
630
PCC FTM7 Register (PCC_​​FTM7)
632
PCC CMP0 Register (PCC_​​CMP0)
633
PCC QSPI Register (PCC_​​QSPI)
635
PCC ENET Register (PCC_​​ENET)
636
Chapter 28​: Clock Monitoring Unit (CMU)
639
Introduction
639
register descriptions
640
CMU Memory map
640
CMU Frequency Check Global Configuration Register (CMU_​​FCGC​R)
641
CMU Frequency Check Reference Count Configuration Register (CMU_​​FCRC​CR)
642
CMU Frequency Check High Threshold Configuration Register (CMU_​​FCHT​CR)
643
CMU Frequency Check Low Threshold Configuration Register (CMU_​​FCLT​CR)
644
CMU Frequency Check Status Register (CMU_​​FCSR)
645
CMU Frequency Check Interrupt/Event Enable Register (CMU_​​FCIE​R)
646
Functional Description
647
Programming Guidelines
648
Chapters 29-34 Memories and Memory Interfaces
651
Chapter 29​: Memories and Memory Interfaces
651
Introduction
651
Flash Memory Controller and flash memory modules
651
SRAM configuration
651
SRAM sizes
652
SRAM accessibility
653
SRAM arbitration and priority control
654
SRAM retention: power modes and resets
654
Chapter 30​: Local Memory Controller (LMEM)
655
Chip-specific LMEM information
655
LMEM region description
655
LMEM SRAM sizes
655
Introduction
655
Block Diagram
655
Cache features
657
Memory Map/Register Definition
659
LMEM register descriptions
659
LMEM Memory map
659
Cache control register (PCCC​R)
659
Cache line control register (PCCL​CR)
661
Cache search address register (PCCS​AR)
663
Cache read/write value register (PCCC​VR)
664
Cache regions mode register (PCCR​MR)
665
Functional Description
668
LMEM Function
668
SRAM Function
669
SRAM Configuration
669
SRAM Arrays
670
SRAM Accesses
670
Cache Function
671
Cache Control
672
Cache set commands
672
Cache line commands
673
Chapter 31​: Miscellaneous System Control Module (MSCM)
677
Chip-specific MSCM information
677
Chip-specific TMLSZ/TMUSZ information
677
Chip-specific register information
677
Overview
678
Chip Configuration and Boot
678
MSCM Memory Map/Register Definition
678
CPU Configuration Memory Map and Registers
678
MSCM register descriptions
679
MSCM Memory map
679
Processor X Type Register (CPxT​YPE)
680
Processor X Number Register (CPxN​UM)
681
Processor X Master Register (CPxM​ASTE​R)
682
Processor X Count Register (CPxC​OUNT)
683
Processor X Configuration Register 0 (CPxC​FG0)
684
Processor X Configuration Register 1 (CPxC​FG1)
686
Processor X Configuration Register 2 (CPxC​FG2)
687
Processor X Configuration Register 3 (CPxC​FG3)
689
Processor 0 Type Register (CP0T​YPE)
690
Processor 0 Number Register (CP0N​UM)
691
Processor 0 Master Register (CP0M​ASTE​R)
692
Processor 0 Count Register (CP0C​OUNT)
693
Processor 0 Configuration Register 0 (CP0C​FG0)
694
Processor 0 Configuration Register 1 (CP0C​FG1)
696
Processor 0 Configuration Register 2 (CP0C​FG2)
697
Processor 0 Configuration Register 3 (CP0C​FG3)
698
On-Chip Memory Descriptor Register (OCMD​R0)
700
On-Chip Memory Descriptor Register (OCMD​R1)
703
On-Chip Memory Descriptor Register (OCMD​R2)
706
Chapter 32​: Flash Memory Controller (FMC)
711
Chip-specific FMC information
711
FMC masters
711
Introduction
712
Overview
712
Features
712
Modes of operation
713
External signal description
713
Functional description
713
Default configuration
713
Speculative reads
714
Initialization and application information
715
Chapter 33​: Flash Memory Module (FTFC)
717
Chip-specific FTFC information
717
Flash memory types
717
Flash memory sizes
718
Flash memory map
718
Flash memory security
719
Power mode restrictions on flash memory programming
719
Flash memory modes
719
Erase all contents of flash memory
719
Customize MCU operations via FTFC_FOPT register
720
Simultaneous operations on PFLASH read partitions
720
Introduction
720
Features
722
Program flash memory features
722
FlexNVM memory features
723
FlexRAM features
723
Cryptographic Services Engine (CSEc) module features
724
Other FTFC module features
724
Block diagram
724
Glossary
729
External signal description
732
Memory map and registers
732
Flash configuration field description
732
Program flash 0 IFR map
733
Program Once field
733
Data flash 0 IFR map
733
EEPROM data set size
734
FlexNVM partition code
734
Register descriptions
734
FTFC register descriptions
735
FTFC Memory map
735
Flash Status Register (FSTA​T)
736
Flash Configuration Register (FCNF​G)
737
Flash Security Register (FSEC)
739
Flash Option Register (FOPT)
740
Flash Common Command Object Registers (FCCO​B3 - FCCO​B8)
741
Program Flash Protection Registers (FPRO​T3 - FPRO​T0)
743
EEPROM Protection Register (FEPR​OT)
746
Data Flash Protection Register (FDPR​OT)
747
Flash CSEc Status Register (FCSE​STAT)
748
Flash Error Status Register (FERS​TAT)
750
Flash Error Configuration Register (FERC​NFG)
751
Functional description
752
Flash protection
752
FlexNVM description
754
FlexNVM block partitioning for FlexRAM
754
EEPROM user perspective
755
EEPROM implementation overview
756
Write endurance to FlexRAM for emulated EEPROM
757
Interrupts
757
Flash operation in low-power modes
757
Wait mode
757
Stop mode
758
Functional modes of operation
758
Flash memory reads and ignored writes
758
Read while write (RWW)
758
Flash program and erase
759
FTFC command operations
759
Command write sequence
760
Load the FCCOB registers
760
Launch the command by clearing CCIF
760
Command execution and error reporting
760
Flash commands
762
Flash commands by mode
765
Allowed simultaneous flash operations
766
Margin read commands
766
Flash command descriptions
767
Read 1s Block command
768
Read 1s Section command
769
Program Check command
770
Program Phrase command
772
Erase Flash Block command
773
Erase Flash Sector command
774
Suspending an Erase Flash Sector operation
775
Resuming a suspended Erase Flash Sector operation
775
Aborting a suspended Erase Flash Sector operation
776
Program Section command
777
Flash sector programming
779
Read 1s All Blocks command
779
Read Once command
780
Program Once command
781
Erase All Blocks command
783
Triggering an erase all external to the flash module
783
Verify Backdoor Access Key command
784
Erase All Blocks Unsecure command
785
Program Partition command
786
Set FlexRAM Function command
790
Security
793
FTFC access by mode and security
793
Changing the security state
793
Un-securing the MCU using backdoor key access
794
Cryptographic Services Engine (CSEc)
795
Key/seed/random number generation
797
Secure boot mode
798
User CSEc command interface and command set
799
CSEc command header
801
Generic PRAM interface description
803
CMD_ENC_ECB
805
CMD_ENC_CBC
806
CMD_DEC_ECB
808
CMD_DEC_CBC
809
CMD_GENERATE_MAC
811
CSEc format for CMD_GENERATE_MAC (pointer method)
812
CMD_VERIFY_MAC
813
CMD_VERIFY_MAC - CSEc format (pointer method)
815
CMD_LOAD_KEY
816
CMD_LOAD_PLAIN_KEY
818
CMD_EXPORT_RAM_KEY
819
CMD_INIT_RNG
821
CMD_EXTEND_SEED
821
CMD_RND
822
CMD_SECURE_BOOT
823
CMD_BOOT_FAILURE
824
CMD_BOOT_OK
825
CMD_GET_STATUS
826
CMD_GET_ID
826
CMD_CANCEL
827
CMD_BOOT_DEFINE
827
CMD_DBG_CHAL
829
CMD_DBG_AUTH
830
CMD_MP_COMPRESS
831
Reset sequence
833
Chapter 34​: Quad Serial Peripheral Interface (QuadSPI)
835
Chip-specific QuadSPI information
835
Overview
835
Memory size requirement
835
QuadSPI register reset values
835
Use case
836
Supported read modes
836
External memory options
837
Recommended software configuration
837
Recommended programming sequence
838
Clock ratio between QuadSPI clocks
838
QuadSPI_MCR[SCLKCFG] implementation
838
QuadSPI_SOCCR[SOCCFG] implementation
839
Introduction
841
Features
841
Block Diagram
842
QuadSPI Modes of Operation
843
Acronyms and Abbreviations
844
Glossary for QuadSPI module
844
External Signal Description
846
Driving External Signals
847
Memory Map and Register Definition
849
Register Write Access
849
Peripheral Bus Register Descriptions
850
QuadSPI
850
QuadSPI_MCR
856
QuadSPI_IPCR
860
QuadSPI_FLSHCR
861
QuadSPI_BUF0CR
862
QuadSPI_BUF1CR
863
QuadSPI_BUF2CR
863
QuadSPI_BUF3CR
864
QuadSPI_BFGENCR
865
QuadSPI_SOCCR
866
QuadSPI_BUF0IND
867
QuadSPI_BUF1IND
867
QuadSPI_BUF2IND
868
QuadSPI_SFAR
869
QuadSPI_SFACR
869
QuadSPI_SMPR
870
QuadSPI_RBSR
872
QuadSPI_RBCT
872
QuadSPI_TBSR
874
QuadSPI_TBDR
874
QuadSPI_TBCT
875
QuadSPI_SR
876
QuadSPI_FR
879
QuadSPI_RSER
882
QuadSPI_SPNDST
885
QuadSPI_SPTRCLR
887
QuadSPI_SFA1AD
888
QuadSPI_SFA2AD
888
QuadSPI_SFB1AD
889
QuadSPI_SFB2AD
889
QuadSPI_RBDRn
890
QuadSPI_LUTKEY
891
QuadSPI_LCKCR
891
QuadSPI_LUTn
892
Serial Flash Address Assignment
893
Flash memory mapped AMBA bus
894
AHB Bus Access Considerations
895
Memory Mapped Serial Flash Data - Individual Flash Mode on Flash A
895
Memory Mapped Serial Flash Data - Individual Flash Mode on Flash B
896
AHB RX Data Buffer (QSPI_ARDB0 to QSPI_ARDB31)
897
ARDBn
897
Interrupt Signals
899
Functional Description
900
Serial Flash Access Schemes
900
Normal Mode
900
Programmable Sequence Engine
901
Flexible AHB buffers
903
Suspend-Abort Mechanism
904
HBURST Support
905
Look-up Table
906
Issuing Serial Flash Memory (SFM) Commands
908
Flash Programming
909
Flash Read
910
Byte Ordering of Serial Flash Read Data
914
Normal Mode Interrupt and DMA Requests
915
TX Buffer Operation
917
Address scheme
918
HyperRAM Support
919
Initialization/Application Information
920
Power Up and Reset
920
Available Status/Flag Information
920
IP Commands
921
AHB Commands
921
Overview of Error Flags
921
IP Bus and AHB Access Command Collisions
923
Exclusive Access to Serial Flash for AHB Commands
923
RX Buffer Read via QSPI_ARDB Registers
923
RX Buffer Read via QSPI_RBDR Registers
924
Command Arbitration
924
Flash Device Selection
925
DMA Usage
925
DMA Usage in Normal Mode
925
Bandwidth considerations
925
Byte Ordering - Endianness
929
Programming Flash Data
930
Reading Flash Data into the RX Buffer
931
Readout of the RX Buffer via QSPI_RBDRn
931
Readout of the RX Buffer via ARDBn
931
Reading Flash Data into the AHB Buffer
932
Readout of the AHB Buffer via Memory Mapped Read
932
Driving Flash Control Signals in Single and Dual Mode
932
Serial Flash Devices
933
Example Sequences
933
Read Command (Spansion Hyperflash/HyperRAM)
933
Read Status Register(Spansion Hyperflash/HyperRAM)
934
Word Program (Spansion Hyperflash/HyperRAM)
934
Fast Read Sequence (Macronix/Numonyx/Spansion/Winbond)
936
Fast Dual I/O DT Read Sequence (Macronix)
936
Fast Read Quad Output (Winbond)
937
4 x I/O Read Enhance Performance Mode (XIP) (Macronix)
937
Dual Command Page Program (Numonyx)
938
Sector Erase (Macronix/Spansion/Numonyx)
938
Read Status Register (Macronix/Spansion/Numonyx/Winbond)
938
Sampling of Serial Flash Input Data
939
Basic Description
939
Supported read modes
940
SDR mode
940
Internal sampling
940
DQS sampling method
942
DDR Mode
942
DQS sampling method
942
Data Strobe (DQS) sampling method
942
Basic Description
942
Internally generated DQS
944
External DQS
944
Data Input Hold Requirement of Flash
946
Chapters 35-37 Power Management
947
Chapter 35​: Power Management
947
Introduction
947
Power modes description
947
Entering and exiting power modes
949
Clocking modes
949
Clock gating
949
Stop mode options
949
DMA wake-up
950
Compute Operation (CPO)
951
Peripheral Doze
952
Power mode transitions
953
Shutdown sequencing for power modes
954
Power mode restrictions on flash memory programming
954
Module operation in available low power modes
954
QuadSPI, Ethernet, and SAI operation
958
Chapter 36​: System Mode Controller (SMC)
959
Introduction
959
Modes of operation
959
Memory map and register descriptions
961
SMC
961
SMC_VERID
961
SMC_PARAM
962
SMC_PMPROT
963
SMC_PMCTRL
965
SMC_ STOPCTRL
967
SMC_PMSTAT
968
Functional description
969
Power mode transitions
969
Power mode entry/exit sequencing
970
VLPS/Stop mode entry sequence
971
VLPS/Stop mode exit sequence
972
Aborted very low power stop mode entry
972
Transition from stop modes to Debug mode
972
Run modes
972
RUN mode
973
Very-Low Power Run (VLPR) mode
973
High Speed Run (HSRUN) mode
974
Stop modes
974
STOP mode
975
Very-Low-Power Stop (VLPS) mode
975
Debug in low power modes
976
Chapter 37​: Power Management Controller (PMC)
977
Chip-specific PMC information
977
Modes supported
977
Introduction
977
Features
977
Modes of Operation
977
Full Performance Mode (FPM)
977
Low Power Mode (LPM)
978
Low Voltage Detect (LVD) System
978
Low Voltage Reset (LVR) Operation
978
LVD Interrupt Operation
979
Low-voltage warning (LVW) interrupt operation
979
Memory Map and Register Definition
979
PMC register descriptions
979
PMC Memory map
980
Low Voltage Detect Status and Control 1 Register (LVDS​C1)
980
Low Voltage Detect Status and Control 2 Register (LVDS​C2)
981
Regulator Status and Control Register (REGS​C)
982
Low Power Oscillator Trim Register (LPOT​RIM)
984
Chapters 38-40 Analog Modules
987
Chapter 38​: ADC Configuration
987
Instantiation information
987
ADC Connections/Channel Assignment
988
Register implementation
989
DMA Support on ADC
989
ADC Hardware Interleaved Channels
990
ADC internal supply monitoring
991
ADC Reference Options
991
ADC Trigger Sources
991
PDB triggering scheme
993
TRGMUX trigger scheme
994
Trigger Selection
995
Trigger Latching and Arbitration
996
ADC low-power modes
998
ADC Trigger Concept – Use Case
998
ADC calibration scheme
1000
Chapter 39​: Analog-to-Digital Converter (ADC)
1003
Chip-specific ADC information
1003
Introduction
1003
Features
1003
Block diagram
1004
ADC signal descriptions
1005
Analog Power (VDDA)
1005
Analog Ground (VSSA)
1005
Voltage Reference Select
1005
Analog Channel Inputs (ADx)
1006
ADC register descriptions
1006
ADC Memory map
1006
ADC Status and Control Register 1 (SC1A - aSC1​P)
1008
ADC Configuration Register 1 (CFG1)
1012
ADC Configuration Register 2 (CFG2)
1013
ADC Data Result Registers (RA - aRP)
1014
Compare Value Registers (CV1 - CV2)
1016
Status and Control Register 2 (SC2)
1017
Status and Control Register 3 (SC3)
1020
BASE Offset Register (BASE​_​OFS)
1021
ADC Offset Correction Register (OFS)
1022
USER Offset Correction Register (USR_​​OFS)
1023
ADC X Offset Correction Register (XOFS)
1024
ADC Y Offset Correction Register (YOFS)
1025
ADC Gain Register (G)
1026
ADC User Gain Register (UG)
1027
ADC General Calibration Value Register S (CLPS)
1028
ADC Plus-Side General Calibration Value Register 3 (CLP3)
1030
ADC Plus-Side General Calibration Value Register 2 (CLP2)
1030
ADC Plus-Side General Calibration Value Register 1 (CLP1)
1031
ADC Plus-Side General Calibration Value Register 0 (CLP0)
1032
ADC Plus-Side General Calibration Value Register X (CLPX)
1033
ADC Plus-Side General Calibration Value Register 9 (CLP9)
1034
ADC General Calibration Offset Value Register S (CLPS​_​OFS)
1035
ADC Plus-Side General Calibration Offset Value Register 3 (CLP3​_​OFS)
1036
ADC Plus-Side General Calibration Offset Value Register 2 (CLP2​_​OFS)
1037
ADC Plus-Side General Calibration Offset Value Register 1 (CLP1​_​OFS)
1038
ADC Plus-Side General Calibration Offset Value Register 0 (CLP0​_​OFS)
1039
ADC Plus-Side General Calibration Offset Value Register X (CLPX​_​OFS)
1040
ADC Plus-Side General Calibration Offset Value Register 9 (CLP9​_​OFS)
1041
ADC Status and Control Register 1 (SC1Q - SC1A​F)
1042
ADC Data Result Registers (RQ - RAF)
1045
Functional description
1046
Clock select and divide control
1046
Voltage reference selection
1047
Hardware trigger and channel selects
1047
Conversion control
1048
Initiating conversions
1048
Completing conversions
1049
Aborting conversions
1050
Power control
1050
Sample time and total conversion time
1051
Hardware average function
1051
Automatic compare function
1052
Calibration function
1053
User-defined offset function
1054
MCU Normal Stop mode operation
1055
Normal Stop mode with Alternate clock sources enabled
1055
Chapter 40​: Comparator (CMP)
1057
Chip-specific CMP information
1057
Instantiation information
1057
CMP input connections
1057
CMP external references
1058
External window/sample input
1058
CMP trigger mode
1058
Programming recommendation
1059
Introduction
1059
Features
1060
CMP features
1060
8-bit DAC key features
1061
ANMUX key features
1061
CMP, DAC, and ANMUX diagram
1061
CMP block diagram
1062
CMP pin descriptions
1064
External pins
1064
CMP functional modes
1065
Disabled mode (# 1)
1066
Continuous mode (#s 2A & 2B)
1066
Sampled, Non-Filtered mode (#s 3A & 3B)
1067
Sampled, Filtered mode (#s 4A & 4B)
1069
Windowed mode (#s 5A & 5B)
1071
Windowed/Resampled mode (# 6)
1073
Windowed/Filtered mode (#7)
1074
Memory map/register definitions
1075
CMP
1075
CMP_C0
1075
CMP_C1
1079
CMP_C2
1082
CMP functional description
1084
Initialization
1084
Low-pass filter
1085
Enabling filter modes
1085
Latency issues
1086
Interrupts
1087
DMA support
1087
DAC functional description
1088
Digital-to-analog converter block diagram
1088
Voltage reference source select
1088
DAC resets
1089
DAC clocks
1089
DAC interrupts
1089
Trigger mode
1089
Chapters 41-45 Timer Modules
1093
Chapter 41​: Programmable delay block (PDB)
1093
Chip-specific PDB information
1093
Instantiation Information
1093
PDB trigger interconnections with ADC and TRGMUX
1094
Back-to-back acknowledgement connections
1094
Pulse-Out Enable Register Implementation
1101
Introduction
1101
Features
1101
Implementation
1102
Back-to-back acknowledgment connections
1102
Block diagram
1103
Modes of operation
1104
Memory map and register definition
1104
PDB
1104
PDB_SC
1106
PDB_MOD
1109
PDB_CNT
1110
PDB_IDLY
1110
PDB_CHnC1
1111
PDB_CHnS
1112
PDB_CHnDLY0
1112
PDB_CHnDLY1
1113
PDB_CHnDLY2
1114
PDB_CHnDLY3
1114
PDB_CHnDLY4
1115
PDB_CHnDLY5
1116
PDB_CHnDLY6
1116
PDB_CHnDLY7
1117
PDB_POEN
1117
PDB_POnDLY
1118
Functional description
1118
PDB pre-trigger and trigger outputs
1118
PDB trigger input source selection
1120
Pulse-Out's
1121
Updating the delay registers
1122
Interrupts
1124
DMA
1124
Application information
1124
Impact of using the prescaler and multiplication factor on timing resolution
1124
Chapter 42​: FlexTimer Module (FTM)
1127
Chip-specific FTM information
1127
Instantiation Information
1127
FTM Interrupts
1128
FTM Fault Detection Inputs
1128
FTM Hardware Triggers and Synchronization
1130
FTM Input Capture Options
1132
FTM Hall sensor support
1133
FTM Modulation Implementation
1133
FTM Global Time Base
1134
FTM BDM and debug halt mode
1135
Introduction
1135
FlexTimer philosophy
1135
Features
1136
Modes of operation
1138
Block Diagram
1138
FTM signal descriptions
1141
Memory map and register definition
1141
Memory map
1141
Register descriptions
1142
FTM register descriptions
1142
FTM Memory map
1142
Status And Control (SC)
1144
Counter (CNT)
1147
Modulo (MOD)
1148
Channel (n) Status And Control (C0SC - C7SC)
1149
Channel (n) Value (C0V - C7V)
1151
Counter Initial Value (CNTI​N)
1152
Capture And Compare Status (STAT​US)
1153
Features Mode Selection (MODE)
1155
Synchronization (SYNC)
1157
Initial State For Channels Output (OUTI​NIT)
1159
Output Mask (OUTM​ASK)
1161
Function For Linked Channels (COMB​INE)
1163
Deadtime Configuration (DEAD​TIME)
1167
FTM External Trigger (EXTT​RIG)
1168
Channels Polarity (POL)
1170
Fault Mode Status (FMS)
1172
Input Capture Filter Control (FILT​ER)
1175
Fault Control (FLTC​TRL)
1176
Quadrature Decoder Control And Status (QDCT​RL)
1179
Configuration (CONF)
1181
FTM Fault Input Polarity (FLTP​OL)
1183
Synchronization Configuration (SYNC​ONF)
1184
FTM Inverting Control (INVC​TRL)
1187
FTM Software Output Control (SWOC​TRL)
1188
FTM PWM Load (PWML​OAD)
1190
Half Cycle Register (HCR)
1192
Pair 0 Deadtime Configuration (PAIR​0DEA​DTIM​E)
1193
Pair 1 Deadtime Configuration (PAIR​1DEA​DTIM​E)
1194
Pair 2 Deadtime Configuration (PAIR​2DEA​DTIM​E)
1196
Pair 3 Deadtime Configuration (PAIR​3DEA​DTIM​E)
1197
Mirror of Modulo Value (MOD_​​MIRR​OR)
1198
Mirror of Channel (n) Match Value (C0V_​​MIRR​OR - C7V_​​MIRR​OR)
1199
Functional Description
1201
Clock source
1201
Counter clock source
1201
Prescaler
1201
Counter
1202
Up counting
1202
Up-down counting
1205
Free running counter
1207
Counter reset
1207
Counter events
1207
Channel Modes
1208
Input Capture Mode
1210
Filter for Input Capture Mode
1211
FTM Counter Reset in Input Capture Mode
1214
Output Compare mode
1215
Edge-Aligned PWM (EPWM) mode
1216
Center-Aligned PWM (CPWM) mode
1218
Combine mode
1220
Asymmetrical PWM
1228
Modified Combine PWM Mode
1228
Synchronization
1231
Complementary Mode
1231
Registers updated from write buffers
1232
CNTIN register update
1233
MOD and HCR registers update
1233
CnV register update
1233
PWM synchronization
1234
Hardware trigger
1234
Software trigger
1235
Synchronization Points
1236
MOD register synchronization
1237
CNTIN register synchronization
1240
C(n)V and C(n+1)V register synchronization
1241
OUTMASK register synchronization
1241
INVCTRL register synchronization
1244
SWOCTRL register synchronization
1245
FTM counter synchronization
1247
Inverting
1250
Software Output Control Mode
1251
Deadtime insertion
1253
Separated Deadtime by Pair of Channels
1254
Deadtime insertion corner cases
1255
Output mask
1257
Fault Control
1258
Automatic fault clearing
1261
Manual fault clearing
1261
Fault inputs polarity control
1262
Polarity Control
1262
Initialization
1263
Features Priority
1263
External Trigger
1264
Initialization Trigger
1265
Capture Test Mode
1267
DMA
1268
Dual Edge Capture Mode
1269
One-Shot Capture mode
1271
Continuous Capture mode
1271
Pulse width measurement
1271
Period measurement
1274
Read coherency mechanism
1276
Quadrature Decoder Mode
1277
Quadrature Decoder boundary conditions
1281
Debug mode
1283
Reload Points
1284
Reload Opportunities
1284
Frequency of Reload Opportunities
1286
Update of the Registers
1286
Global Load
1287
Global time base (GTB)
1288
Enabling the global time base (GTB)
1289
Channel trigger output
1289
External Control of Channels Output
1290
Dithering
1290
PWM Period Dithering
1291
Up Counting
1291
Up-Down Counting
1293
PWM Edge Dithering
1294
EPWM Mode
1294
CPWM Mode
1296
Combine Mode
1297
Modified Combine PWM Mode
1299
Reset Overview
1301
FTM Interrupts
1303
Timer Overflow Interrupt
1303
Reload Point Interrupt
1303
Channel (n) Interrupt
1303
Fault Interrupt
1303
Initialization Procedure
1304
Chapter 43​: Low Power Interrupt Timer (LPIT)
1307
Chip-specific LPIT information
1307
Instantiation Information
1307
LPIT/DMA Periodic Trigger Assignments
1307
LPIT input triggers
1308
LPIT/ADC Trigger
1308
Introduction
1309
Modes of operation
1311
Memory Map and Registers
1312
LPIT register descriptions
1312
LPIT Memory map
1312
Version ID Register (VERI​D)
1313
Parameter Register (PARA​M)
1313
Module Control Register (MCR)
1314
Module Status Register (MSR)
1316
Module Interrupt Enable Register (MIER)
1317
Set Timer Enable Register (SETT​EN)
1318
Clear Timer Enable Register (CLRT​EN)
1319
Timer Value Register (TVAL​0 - TVAL​3)
1321
Current Timer Value (CVAL​0 - CVAL​3)
1322
Timer Control Register (TCTR​L0 - TCTR​L3)
1323
Functional description
1325
Detailed timing
1328
Chapter 44​: Low Power Timer (LPTMR)
1341
Chip-specific LPTMR information
1341
Instantiation Information
1341
LPTMR pulse counter input options
1341
Introduction
1342
Features
1342
Modes of operation
1342
LPTMR signal descriptions
1343
Detailed signal descriptions
1343
Memory map and register definition
1343
LPTMR register descriptions
1343
LPTMR Memory map
1344
Low Power Timer Control Status Register (CSR)
1344
Low Power Timer Prescale Register (PSR)
1345
Low Power Timer Compare Register (CMR)
1347
Low Power Timer Counter Register (CNR)
1348
Functional description
1349
LPTMR power and reset
1349
LPTMR clocking
1349
LPTMR prescaler/glitch filter
1350
Prescaler enabled
1350
Prescaler bypassed
1350
Glitch filter
1350
Glitch filter bypassed
1351
LPTMR compare
1351
LPTMR counter
1351
LPTMR hardware trigger
1352
LPTMR interrupt
1352
Chapter 45​: Real Time Clock (RTC)
1355
Chip-specific RTC information
1355
RTC instantiation
1355
RTC interrupts
1355
Software recommendation
1355
Introduction
1355
Features
1356
Modes of operation
1356
RTC signal descriptions
1356
RTC clock output
1356
Register definition
1357
RTC register descriptions
1357
RTC Memory map
1357
RTC Time Seconds Register (TSR)
1357
RTC Time Prescaler Register (TPR)
1358
RTC Time Alarm Register (TAR)
1359
RTC Time Compensation Register (TCR)
1360
RTC Control Register (CR)
1361
RTC Status Register (SR)
1363
RTC Lock Register (LR)
1364
RTC Interrupt Enable Register (IER)
1365
Functional description
1367
Power, clocking, and reset
1367
Oscillator control
1367
Software reset
1367
Supervisor access
1368
Time counter
1368
Compensation
1369
Time alarm
1369
Update mode
1370
Register lock
1370
Interrupt
1370
Chapter 46-52 Communication Modules
1371
Chapter 46​: Low Power Serial Peripheral Interface (LPSPI)
1371
Chip-specific LPSPI information
1371
Instantiation Information
1371
Introduction
1372
Features
1372
Block Diagram
1372
Modes of operation
1373
Signal Descriptions
1373
Memory Map and Registers
1374
LPSPI register descriptions
1374
LPSPI Memory map
1374
Version ID Register (VERI​D)
1375
Parameter Register (PARA​M)
1376
Control Register (CR)
1377
Status Register (SR)
1378
Interrupt Enable Register (IER)
1380
DMA Enable Register (DER)
1381
Configuration Register 0 (CFGR​0)
1382
Configuration Register 1 (CFGR​1)
1383
Data Match Register 0 (DMR0)
1385
Data Match Register 1 (DMR1)
1386
Clock Configuration Register (CCR)
1387
FIFO Control Register (FCR)
1388
FIFO Status Register (FSR)
1389
Transmit Command Register (TCR)
1390
Transmit Data Register (TDR)
1394
Receive Status Register (RSR)
1394
Receive Data Register (RDR)
1395
Functional description
1396
Clocking and Resets
1396
Master Mode
1397
Slave Mode
1402
Interrupts and DMA Requests
1404
Peripheral Triggers
1405
Chapter 47​: Low Power Inter-Integrated Circuit (LPI2C)
1407
Chip-specific LPI2C information
1407
Instantiation information
1407
Introduction
1408
Features
1408
Block Diagram
1410
Modes of operation
1410
Signal Descriptions
1411
Wiring options
1411
Memory Map and Registers
1413
LPI2C register descriptions
1413
LPI2C Memory map
1413
Version ID Register (VERI​D)
1414
Parameter Register (PARA​M)
1415
Master Control Register (MCR)
1416
Master Status Register (MSR)
1418
Master Interrupt Enable Register (MIER)
1420
Master DMA Enable Register (MDER)
1421
Master Configuration Register 0 (MCFG​R0)
1422
Master Configuration Register 1 (MCFG​R1)
1424
Master Configuration Register 2 (MCFG​R2)
1426
Master Configuration Register 3 (MCFG​R3)
1427
Master Data Match Register (MDMR)
1428
Master Clock Configuration Register 0 (MCCR​0)
1429
Master Clock Configuration Register 1 (MCCR​1)
1430
Master FIFO Control Register (MFCR)
1432
Master FIFO Status Register (MFSR)
1433
Master Transmit Data Register (MTDR)
1434
Master Receive Data Register (MRDR)
1435
Slave Control Register (SCR)
1436
Slave Status Register (SSR)
1437
Slave Interrupt Enable Register (SIER)
1440
Slave DMA Enable Register (SDER)
1441
Slave Configuration Register 1 (SCFG​R1)
1442
Slave Configuration Register 2 (SCFG​R2)
1445
Slave Address Match Register (SAMR)
1446
Slave Address Status Register (SASR)
1447
Slave Transmit ACK Register (STAR)
1448
Slave Transmit Data Register (STDR)
1449
Slave Receive Data Register (SRDR)
1451
Functional description
1452
Clocking and Resets
1452
Master Mode
1452
Slave Mode
1458
Interrupts and DMA Requests
1461
Peripheral Triggers
1463
Chapter 48​: Low Power Universal Asynchronous Receiver/Transmitter (LPUART)
1465
Chip-specific LPUART information
1465
Instantiation Information
1465
Introduction
1466
Features
1466
Modes of operation
1467
Signal Descriptions
1467
Block diagram
1467
Register definition
1469
LPUART register descriptions
1469
LPUART Memory map
1469
Version ID Register (VERI​D)
1470
Parameter Register (PARA​M)
1471
LPUART Global Register (GLOB​AL)
1472
LPUART Pin Configuration Register (PINC​FG)
1473
LPUART Baud Rate Register (BAUD)
1473
LPUART Status Register (STAT)
1476
LPUART Control Register (CTRL)
1480
LPUART Data Register (DATA)
1484
LPUART Match Address Register (MATC​H)
1486
LPUART Modem IrDA Register (MODI​R)
1487
LPUART FIFO Register (FIFO)
1489
LPUART Watermark Register (WATE​R)
1492
Functional description
1494
Baud rate generation
1494
Transmitter functional description
1495
Send break and queued idle
1496
Hardware flow control
1497
Transceiver driver enable
1497
Transceiver driver enable using RTS_B
1498
Receiver functional description
1498
Data sampling technique
1499
Receiver wakeup operation
1500
Idle-line wakeup
1501
Address-mark wakeup
1502
Data match wakeup
1502
Address Match operation
1502
Idle Match operation
1503
Match On Match Off operation
1503
Hardware flow control
1504
Infrared decoder
1504
Start bit detection
1504
Noise filtering
1505
Low-bit detection
1505
High-bit detection
1505
Additional LPUART functions
1505
Data Modes
1505
Idle length
1506
Loop mode
1506
Single-wire operation
1507
Infrared interface
1507
Infrared transmit encoder
1508
Infrared receive decoder
1508
Interrupts and status flags
1508
Peripheral Triggers
1509
Chapter 49​: Flexible I/O (FlexIO)
1511
Chip-specific FlexIO information
1511
FlexIO Configuration
1511
Introduction
1511
Features
1512
Block Diagram
1512
Modes of operation
1513
FlexIO Signal Descriptions
1513
Memory Map and Registers
1514
FLEXIO register descriptions
1514
FLEXIO Memory map
1514
Version ID Register (VERI​D)
1515
Parameter Register (PARA​M)
1515
FlexIO Control Register (CTRL)
1516
Pin State Register (PIN)
1518
Shifter Status Register (SHIF​TSTA​T)
1518
Shifter Error Register (SHIF​TERR)
1519
Timer Status Register (TIMS​TAT)
1520
Shifter Status Interrupt Enable (SHIF​TSIE​N)
1521
Shifter Error Interrupt Enable (SHIF​TEIE​N)
1522
Timer Interrupt Enable Register (TIMI​EN)
1523
Shifter Status DMA Enable (SHIF​TSDE​N)
1524
Shifter Control N Register (SHIF​TCTL​0 - SHIF​TCTL​3)
1525
Shifter Configuration N Register (SHIF​TCFG​0 - SHIF​TCFG​3)
1527
Shifter Buffer N Register (SHIF​TBUF​0 - SHIF​TBUF​3)
1528
Shifter Buffer N Bit Swapped Register (SHIF​TBUF​BIS0 - SHIF​TBUF​BIS3)
1529
Shifter Buffer N Byte Swapped Register (SHIF​TBUF​BYS0 - SHIF​TBUF​BYS3)
1530
Shifter Buffer N Bit Byte Swapped Register (SHIF​TBUF​BBS0 - SHIF​TBUF​BBS3)
1531
Timer Control N Register (TIMC​TL0 - TIMC​TL3)
1532
Timer Configuration N Register (TIMC​FG0 - TIMC​FG3)
1534
Timer Compare N Register (TIMC​MP0 - TIMC​MP3)
1537
Functional description
1538
Clocking and Resets
1538
Shifter operation
1538
Timer Operation
1541
Pin operation
1544
Interrupts and DMA Requests
1545
Peripheral Triggers
1545
Application Information
1545
UART Transmit
1546
UART Receive
1547
SPI Master
1548
SPI Slave
1550
I2C Master
1552
I2S Master
1554
I2S Slave
1555
Chapter 50​: FlexCAN
1559
Chip-specific FlexCAN information
1559
Instantiation information
1559
Reset value of MDIS bit
1560
FlexCAN external time tick
1560
FlexCAN Interrupts
1560
FlexCAN Operation in Low Power Modes
1561
FlexCAN oscillator clock
1561
Introduction
1561
Overview
1562
FlexCAN module features
1563
Modes of operation
1565
FlexCAN signal descriptions
1567
CAN Rx
1567
CAN Tx
1567
Memory map/register definition
1567
FlexCAN memory mapping
1567
CAN register descriptions
1569
CAN Memory map
1569
Module Configuration Register (MCR)
1571
Control 1 register (CTRL​1)
1575
Free Running Timer (TIME​R)
1579
Rx Mailboxes Global Mask Register (RXMG​MASK)
1581
Rx 14 Mask register (RX14​MASK)
1582
Rx 15 Mask register (RX15​MASK)
1583
Error Counter (ECR)
1584
Error and Status 1 register (ESR1)
1587
Interrupt Masks 1 register (IMAS​K1)
1592
Interrupt Flags 1 register (IFLA​G1)
1593
Control 2 register (CTRL​2)
1596
Error and Status 2 register (ESR2)
1600
CRC Register (CRCR)
1602
Rx FIFO Global Mask register (RXFG​MASK)
1603
Rx FIFO Information Register (RXFI​R)
1605
CAN Bit Timing Register (CBT)
1606
Rx Individual Mask Registers (RXIM​R0 - RXIM​R31)
1608
Pretended Networking Control 1 Register (CTRL​1_​PN)
1609
Pretended Networking Control 2 Register (CTRL​2_​PN)
1611
Pretended Networking Wake Up Match Register (WU_​M​TC)
1612
Pretended Networking ID Filter 1 Register (FLT_​​ID1)
1614
Pretended Networking DLC Filter Register (FLT_​​DLC)
1615
Pretended Networking Payload Low Filter 1 Register (PL1_​​LO)
1616
Pretended Networking Payload High Filter 1 Register (PL1_​​HI)
1617
Pretended Networking ID Filter 2 Register / ID Mask Register (FLT_​​ID2_​​IDMA​SK)
1619
Pretended Networking Payload Low Filter 2 Register / Payload Low Mask Register (PL2_​​PLMA​SK_​L​O)
1620
Pretended Networking Payload High Filter 2 low order bits / Payload High Mask Register (PL2_​​PLMA​SK_​H​I)
1622
Wake Up Message Buffer Register for C/S (WMB0​_​CS - WMB3​_​CS)
1623
Wake Up Message Buffer Register for ID (WMB0​_​ID - WMB3​_​ID)
1624
Wake Up Message Buffer Register for Data 0-3 (WMB0​_​D03 - WMB3​_​D03)
1626
Wake Up Message Buffer Register Data 4-7 (WMB0​_​D47 - WMB3​_​D47)
1627
CAN FD Control Register (FDCT​RL)
1628
CAN FD Bit Timing Register (FDCB​T)
1631
CAN FD CRC Register (FDCR​C)
1633
Message buffer structure
1635
FlexCAN Memory Partition for CAN FD
1641
FlexCAN message buffer memory map
1642
Rx FIFO structure
1645
Functional description
1647
Transmit process
1648
Arbitration process
1649
Lowest-number Mailbox first
1650
Highest-priority Mailbox first
1650
Local Priority disabled
1650
Local Priority enabled
1650
Arbitration process (continued)
1651
Receive process
1652
Matching process
1655
Receive Process under Pretended Networking Mode
1659
Move process
1664
Move-in
1664
Move-out
1665
Data coherence
1666
Transmission abort mechanism
1666
Mailbox inactivation
1667
Mailbox lock mechanism
1668
Rx FIFO
1669
Rx FIFO under DMA Operation
1671
Clear FIFO Operation
1672
CAN protocol related features
1672
CAN FD ISO compliance
1672
CAN FD frames
1673
Transceiver Delay Compensation
1678
Remote frames
1680
Overload frames
1681
Time stamp
1681
Protocol timing
1682
Arbitration and matching timing
1687
Tx Arbitration start delay
1688
Clock domains and restrictions
1692
Modes of operation details
1696
Freeze mode
1697
Module Disable mode
1698
Stop mode
1698
Pretended Networking Mode
1699
Interrupts
1700
Bus interface
1701
Initialization/application information
1702
FlexCAN initialization sequence
1702
Chapter 51​: Synchronous Audio Interface (SAI)
1705
Chip-specific SAI information
1705
SAI configuration
1705
Chip-specific register information
1706
Introduction
1706
Features
1706
Block diagram
1707
Modes of operation
1707
External signals
1708
Memory map and register definition
1708
I2S register descriptions
1708
I2S Memory map
1708
Version ID Register (VERI​D)
1709
Parameter Register (PARA​M)
1710
SAI Transmit Control Register (TCSR)
1711
SAI Transmit Configuration 1 Register (TCR1)
1714
SAI Transmit Configuration 2 Register (TCR2)
1715
SAI Transmit Configuration 3 Register (TCR3)
1717
SAI Transmit Configuration 4 Register (TCR4)
1718
SAI Transmit Configuration 5 Register (TCR5)
1720
SAI Transmit Data Register (TDR0 - TDR3)
1721
SAI Transmit FIFO Register (TFR0 - TFR3)
1722
SAI Transmit Mask Register (TMR)
1723
SAI Receive Control Register (RCSR)
1724
SAI Receive Configuration 1 Register (RCR1)
1727
SAI Receive Configuration 2 Register (RCR2)
1728
SAI Receive Configuration 3 Register (RCR3)
1730
SAI Receive Configuration 4 Register (RCR4)
1731
SAI Receive Configuration 5 Register (RCR5)
1734
SAI Receive Data Register (RDR0 - RDR3)
1735
SAI Receive FIFO Register (RFR0 - RFR3)
1736
SAI Receive Mask Register (RMR)
1737
Functional description
1738
SAI clocking
1738
SAI resets
1740
Synchronous modes
1740
Frame sync configuration
1741
Data FIFO
1742
Data alignment
1742
FIFO pointers
1743
FIFO packing
1743
FIFO Combine
1744
Word mask register
1745
Interrupts and DMA requests
1746
FIFO request flag
1746
FIFO warning flag
1746
FIFO error flag
1746
Sync error flag
1747
Word start flag
1747
Chapter 52​: Ethernet MAC (ENET)
1749
Chip-specific ENET information
1749
Introduction
1749
Overview
1750
Features
1750
Ethernet MAC features
1750
IP protocol performance optimization features
1752
IEEE 1588 features
1752
Block diagram
1753
External signal description
1753
Memory map/register definition
1755
ENET
1756
ENET_EIR
1760
ENET_EIMR
1763
ENET_RDAR
1766
ENET_TDAR
1766
ENET_ECR
1767
ENET_MMFR
1769
ENET_MSCR
1770
ENET_MIBC
1772
ENET_RCR
1773
ENET_TCR
1776
ENET_PALR
1778
ENET_PAUR
1778
ENET_OPD
1779
ENET_IAUR
1779
ENET_IALR
1780
ENET_GAUR
1780
ENET_GALR
1781
ENET_TFWR
1781
ENET_RDSR
1782
ENET_TDSR
1783
ENET_MRBR
1784
ENET_RSFL
1785
ENET_RSEM
1785
ENET_RAEM
1786
ENET_RAFL
1786
ENET_TSEM
1787
ENET_TAEM
1787
ENET_TAFL
1788
ENET_TIPG
1788
ENET_FTRL
1789
ENET_TACC
1789
ENET_RACC
1790
ENET_RMON_T_DROP
1791
ENET_RMON_T_PACKETS
1792
ENET_RMON_T_BC_PKT
1792
ENET_RMON_T_MC_PKT
1793
ENET_RMON_T_CRC_ALIGN
1793
ENET_RMON_T_UNDERSIZE
1793
ENET_RMON_T_OVERSIZE
1794
ENET_RMON_T_FRAG
1794
ENET_RMON_T_JAB
1795
ENET_RMON_T_COL
1795
ENET_RMON_T_P64
1795
ENET_RMON_T_P65TO127
1796
ENET_RMON_T_P128TO255
1796
ENET_RMON_T_P256TO511
1797
ENET_RMON_T_P512TO1023
1797
ENET_RMON_T_P1024TO2047
1798
ENET_RMON_T_P_GTE2048
1798
ENET_RMON_T_OCTETS
1798
ENET_IEEE_T_DROP
1799
ENET_IEEE_T_FRAME_OK
1799
ENET_IEEE_T_1COL
1800
ENET_IEEE_T_MCOL
1800
ENET_IEEE_T_DEF
1800
ENET_IEEE_T_LCOL
1801
ENET_IEEE_T_EXCOL
1801
ENET_IEEE_T_MACERR
1802
ENET_IEEE_T_CSERR
1802
ENET_IEEE_T_SQE
1802
ENET_IEEE_T_FDXFC
1803
ENET_IEEE_T_OCTETS_OK
1803
ENET_RMON_R_PACKETS
1804
ENET_RMON_R_BC_PKT
1804
ENET_RMON_R_MC_PKT
1804
ENET_RMON_R_CRC_ALIGN
1805
ENET_RMON_R_UNDERSIZE
1805
ENET_RMON_R_OVERSIZE
1806
ENET_RMON_R_FRAG
1806
ENET_RMON_R_JAB
1806
ENET_RMON_R_RESVD_0
1807
ENET_RMON_R_P64
1807
ENET_RMON_R_P65TO127
1808
ENET_RMON_R_P128TO255
1808
ENET_RMON_R_P256TO511
1808
ENET_RMON_R_P512TO1023
1809
ENET_RMON_R_P1024TO2047
1809
ENET_RMON_R_P_GTE2048
1810
ENET_RMON_R_OCTETS
1810
ENET_IEEE_R_DROP
1810
ENET_IEEE_R_FRAME_OK
1811
ENET_IEEE_R_CRC
1811
ENET_IEEE_R_ALIGN
1812
ENET_IEEE_R_MACERR
1812
ENET_IEEE_R_FDXFC
1812
ENET_IEEE_R_OCTETS_OK
1813
ENET_ATCR
1813
ENET_ATVR
1815
ENET_ATOFF
1816
ENET_ATPER
1816
ENET_ATCOR
1817
ENET_ATINC
1817
ENET_ATSTMP
1818
ENET_TGSR
1818
ENET_TCSRn
1819
ENET_TCCRn
1820
Functional description
1821
Ethernet MAC frame formats
1821
Pause Frames
1823
Magic packets
1823
IP and higher layers frame format
1824
Ethernet types
1824
IPv4 datagram format
1824
IPv6 datagram format
1825
Internet Control Message Protocol (ICMP) datagram format
1826
User Datagram Protocol (UDP) datagram format
1827
TCP datagram format
1827
IEEE 1588 message formats
1828
Transport encapsulation
1828
UDP/IP
1828
Native Ethernet (PTPv2)
1829
PTP header
1829
PTPv1 header
1830
PTPv2 header
1830
MAC receive
1832
Collision detection in half-duplex mode
1833
Preamble processing
1833
MAC address check
1834
Unicast address check
1834
Multicast and unicast address resolution
1834
Broadcast address reject
1835
Miss-bit implementation
1835
Frame length/type verification: payload length check
1836
Frame length/type verification: frame length check
1836
VLAN frames processing
1836
Pause frame termination
1836
CRC check
1837
Frame padding removal
1837
MAC transmit
1838
Frame payload padding
1839
MAC address insertion
1839
CRC-32 generation
1839
Inter-packet gap (IPG)
1840
Collision detection and handling — half-duplex operation only
1840
Full-duplex flow control operation
1842
Remote device congestion
1842
Local device/FIFO congestion
1843
Magic packet detection
1844
Sleep mode
1844
Magic packet detection
1844
Wakeup
1844
IP accelerator functions
1845
Checksum calculation
1845
Additional padding processing
1846
32-bit Ethernet payload alignment
1846
Receive processing
1846
Transmit processing
1847
Received frame discard
1847
IPv4 fragments
1848
IPv6 support
1848
Receive processing
1848
Transmit processing
1849
Resets and stop controls
1849
Hardware reset
1849
Soft reset
1849
Hardware freeze
1850
Graceful stop
1850
Graceful transmit stop (GTS)
1850
Graceful receive stop (GRS)
1851
Graceful stop interrupt (GRA)
1852
IEEE 1588 functions
1852
Adjustable timer module
1853
Adjustable timer implementation
1853
Transmit timestamping
1855
Receive timestamping
1855
Time synchronization
1855
Input Capture and Output Compare
1856
Input capture
1856
Output compare
1856
DMA requests
1856
FIFO thresholds
1856
Receive FIFO
1857
Transmit FIFO
1858
Loopback options
1859
Legacy buffer descriptors
1860
Legacy receive buffer descriptor
1860
Legacy transmit buffer descriptor
1860
Enhanced buffer descriptors
1861
Enhanced receive buffer descriptor
1861
Enhanced transmit buffer descriptor
1865
Client FIFO application interface
1867
Data structure description
1868
Data structure examples
1869
Frame status
1870
FIFO protection
1870
Transmit FIFO underflow
1870
Transmit FIFO overflow
1871
Receive FIFO overflow
1872
Reference clock
1872
PHY management interface
1873
MDIO clause 22 frame format
1873
MDIO clause 45 frame format
1874
MDIO clock generation
1875
MDIO operation
1875
Ethernet interfaces
1876
RMII interface
1876
MII Interface — transmit
1877
Transmit with collision — half-duplex
1878
MII interface — receive
1879
Chapters 53-54 Debug Modules
1881
Chapter 53​: Debug
1881
Introduction
1881
CM4 ROM table
1883
Debug port
1884
Debug port pin descriptions
1885
System TAP connection
1885
JTAG status and control registers
1886
MDM-AP Control Register
1887
MDM-AP Status Register
1888
Debug resets
1889
AHB-AP
1890
ITM
1890
Core trace connectivity
1891
TPIU
1891
DWT
1892
Debug in low-power modes
1892
Debug and security
1893
Chapter 54​: JTAG Controller (JTAGC)
1895
Chip-specific JTAGC information
1895
Introduction
1895
Block diagram
1895
Features
1896
Modes of operation
1896
Reset
1896
IEEE 1149.1-2001 defined test modes
1897
Bypass mode
1897
External signal description
1898
TCK—Test clock input
1898
TDI—Test data input
1898
TDO—Test data output
1898
TMS—Test mode select
1899
Register description
1899
Instruction register
1899
Bypass register
1899
Device identification register
1900
Boundary scan register
1900
Functional description
1901
JTAGC reset configuration
1901
IEEE 1149.1-2001 (JTAG) Test Access Port
1901
TAP controller state machine
1901
Enabling the TAP controller
1903
Selecting an IEEE 1149.1-2001 register
1904
JTAGC block instructions
1904
IDCODE instruction
1905
SAMPLE/PRELOAD instruction
1905
SAMPLE instruction
1905
EXTEST External test instruction
1906
ENABLE_SOC_DATA1 instruction
1906
HIGHZ instruction
1906
CLAMP instruction
1906
BYPASS instruction
1907
Boundary scan
1907
Initialization/Application information
1907
Appendix A: Release Notes for Revision 4
1909
General changes
1909
About This Manual changes
1909
Introduction changes
1909
Memory map changes
1909
Signal multiplexing changes
1910
Security Overview changes
1910
Safety Overview changes
1910
Core overview changes
1910
MCM changes
1910
Chip-specific MCM information changes
1910
MCM changes
1910
SIM changes
1911
Chip-specific SIM information changes
1911
SIM changes
1911
PORT changes
1911
Chip-specific PORT information changes
1911
Port Control and Interrupts (PORT) changes
1911
GPIO changes
1911
Chip-specific GPIO information changes
1911
GPIO module changes
1911
AXBS-Lite changes
1912
Chip-specific AXBS-Lite information changes
1912
AXBS module changes
1912
MPU changes
1912
Chip-specific MPU information changes
1912
MPU module changes
1912
AIPS-Lite changes
1912
Chip-specific AIPS information changes
1912
AIPS-Lite module changes
1912
DMAMUX changes
1913
Chip-specific DMAMUX information changes
1913
DMAMUX module changes
1913
eDMA changes
1913
Chip-specific eDMA information changes
1913
eDMA2 module changes
1913
TRGMUX changes
1913
Chip-specific TRGMUX information changes
1913
TRGMUX module changes
1914
EWM changes
1914
Chip-specific EWM information changes
1914
EWM module changes
1914
EIM changes
1914
Chip-specific EIM information changes
1914
EIM changes
1914
ERM changes
1914
Chip-specific ERM information changes
1914
ERM changes
1915
WDOG changes
1915
Chip-specific WDOG information changes
1915
WDOG module changes
1915
CRC module changes
1915
Reset and Boot changes
1915
RCM changes
1915
Chip-specific RCM information changes
1915
RCM changes
1916
Clock Distribution changes
1916
SCG changes
1916
Chip-specific SCG information changes
1916
SCG changes
1916
PCC changes
1917
Chip-specific PCC information changes
1917
PCC module changes
1917
Memories and memory interfaces changes
1917
LMEM changes
1917
Chip-specific LMEM information changes
1917
LMEM module changes
1917
MSCM changes
1918
Chip-specific MSCM information changes
1918
MSCM changes
1918
FMC changes
1918
Chip-specific FMC changes
1918
FMC changes
1918
FTFC changes
1918
Chip-specific FTFC information changes
1918
FTFC changes
1919
QSPI changes
1919
Chip-specific QSPI information changes
1919
QuadSPI changes
1919
Power Management changes
1919
SMC changes
1920
PMC changes
1920
Chip-specific PMC changes
1920
PMC module changes
1920
ADC Configuration changes
1920
ADC changes
1920
Chip-specific ADC information changes
1920
ADC module changes
1921
CMP changes
1921
Chip-specific CMP changes
1921
CMP changes
1921
PDB changes
1922
Chip-specific PDB information changes
1922
PDB changes
1922
FTM changes
1922
Chip-specific FTM information changes
1922
FTM module changes
1922
LPIT changes
1922
Chip-specific LPIT information changes
1922
LPIT module changes
1923
LPTMR changes
1923
Chip-specific LPTMR information changes
1923
LPTMR module changes
1923
RTC changes
1923
Chip-specific RTC changes
1923
RTC module changes
1923
LPSPI changes
1924
Chip-specific LPSPI information changes
1924
LPSPI module changes
1924
LPI2C changes
1924
Chip-specific LPI2C information changes
1924
LPI2C module changes
1924
LPUART changes
1924
Chip-specific LPUART information changes
1924
LPUART module changes
1924
FlexIO changes
1925
Chip-specific FlexIO changes
1925
FLEXIO module changes
1925
FlexCAN changes
1925
Chip-specific FlexCAN information changes
1925
FlexCAN3_FD module changes
1925
SAI changes
1926
Chip-specific SAI changes
1926
SAI module changes
1926
ENETchanges
1926
Chip-specific ENET changes
1926
ENET module changes
1926
Debug changes
1926
JTAGC changes
1927
Chip-specific JTAGC information changes
1927
JTAGC module changes
1927
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NXP Semiconductors S32K116 Specifications
General
Brand
NXP Semiconductors
Model
S32K116
Category
Semiconductors
Language
English
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