NXP Semiconductors QorIQ T2080 - T2080 RDB-PC Board Features

Table 3. Flash image layout
Start address End address Image Maximum size
0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768 kB
0xEFF20000 0xEFF3FFFF U-Boot environment (current bank) 128 kB
0xEFF00000 0xEFF1FFFF FMan microcode (current bank) 128 kB
0xEFE00000 0xEFE3FFFF PHY CS4315 firmware 256 kB
0xED300000 0xEFEFFFFF rootfs (alternate bank) 44 MB
0xEC800000 0xEC8FFFFF Hardware device tree (alternate bank) 1 MB
0xEC020000 0xEC7FFFFF Linux.uImage (alternate bank) 7 MB + 875 kB
0xEC000000 0xEC01FFFF RCW (alternate bank) 128 kB
0xEBF40000 0xEBFFFFFF U-Boot (alternate bank) 768 kB
0xEBF20000 0xEBF3FFFF U-Boot environment (alternate bank) 128 kB
0xEBF00000 0xEBF1FFFF FMan microcode (alternate bank) 128 kB
0xEBE00000 0xEBE3FFFF PHY CS4315 firmware (alternate bank) 256 kB
0xE9300000 0xEBEFFFFF rootfs (current bank) 44 MB
0xE8800000 0xE88FFFFF Hardware device tree (current bank) 1 MB
0xE8020000 0xE87FFFFF Linux.uImage (current bank) 7 MB + 875 kB
0xE8000000 0xE801FFFF RCW (current bank) 128 kB
6 Default RCW setting
Table 4 shows the default reset configuration word (RCW) settings.
Table 4. Default RCW settings
No RCW words Description
1 0x120c0017
120c: System PLL rate is 1:9 (SYSCLK is 66.66 MHz) and DDR PLL rate
is 1:12 (DDRCLK is 133.33 MHz)
0017: Cluster 1 core PLL rate is 1:23 (SYSCLK is 66.66 MHz)
2 0x15000000
1500: Cluster 2 core PLL rate is 1:21 (SYSCLK is 66.66 MHz)
0000: Reserved
3 0x00000000 Reserved
4 0x00000000 Default setting
5 0x66150002
0x66: SerDes1 protocol is 0x66 (choose four XFI and PCIe x4
on SerDes1)
0x15: SerDes2 protocol is 0x15 (choose one PCIe x4, one PCIe x2, and
two SATA on SerDes2)
0x02: FMan runs 1x frequency of MAC
Table continues on the next page...
NXP Semiconductors
Default RCW setting
QorIQ T2080 Reference Design Board (T2080RDB-PC) Quick Start, Rev. 1, 08/2021
User Guide 6 / 12