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General| Architecture | Power Architecture |
|---|---|
| Core | e6500 |
| Core Count | 8 |
| Process Technology | 28 nm |
| Memory Channels | 2 |
| USB | USB 2.0 |
| L1 Cache | 32 KB instruction, 32 KB data per core |
| Memory Support | DDR3, DDR3L |
| Ethernet | 10 GbE, 1 GbE |
| Security | Secure Boot |
| Operating Temperature | -40 to 105 °C |
Lists related documents for the T2080RDB-PC.
Defines common terms and abbreviations used in the document.
Details the key features of the T2080 processor silicon.
Outlines the specific hardware features of the T2080RDB-PC board.
Provides a high-level block diagram of the T2080RDB-PC system architecture.
Describes the processor features of the T2080.
Details the power supply system and architecture of the T2080RDB-PC.
Explains how reset signals are managed for the T2080 and other devices.
Describes the clock circuitry and its provision for the processor.
Details the DDR memory interface and its support for high-speed DRAM.
Covers the SerDes block, 16 high-speed serial communication lanes.
Covers the two Ethernet controllers connecting to Ethernet PHYs.
Details the two Ethernet Management Interfaces (EMI) and their usage.
Explains the four I2C buses and their subsystem.
Describes the SPI pins used for onboard SPI device access.
Details the Integrated Flash Controller (IFC) and its local bus support.
Describes the enhanced SD Host Controller (eSDHC) for SD card interface.
Details the two integrated USB 2.0 controllers and their board features.
Explains the two UART controllers providing RS-232 interconnection.
Describes the JTAG module for system debugging and emulation.
Covers various connectors, headers, jumpers, buttons, and LEDs on the board.
Details the thermal diode and temperature monitoring capabilities.
Explains the user-selectable DIP switches for boot configurations.
Explains the registers within the CPLD.
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