NXP Semiconductors QorIQ T2080 - Chapter 3 CPLD Specification; Register Descriptions

Chapter 3
CPLD Specification
This section explains the CPLD registers.
3.1 Register descriptions
3.1.1 CPLD Memory map
T2080_RDB base address: 0h
Offset Register
Width
(In bits)
Access Reset value
0h Chip ID1 register (CHIPID1) 8 RO 55h
1h Chip ID2 register (CHIPID2) 8 RO AAh
2h Hardware version register (HWVER) 8 RO See description
3h Software version register (SWVER) 8 RO See description
10h Reset control register (RSTCON) 8 W1C See description
11h Flash control and status register (FLHCSR) 8 RW See description
12h Thermal control and status register (THMCSR) 8 RW See description
13h Panel LED control and status register (LEDCSR) 8 RW 00h
14h SFP+ control and status register (SFPCSR) 8 RW See description
15h Miscellanies control and status register (MISCCSR) 8 RW See description
16h Boot configuration override register (BOOTOR) 8 RW 00h
17h Boot configuration register 1 (BOOTCFG1) 8 RW 00h
18h Boot configuration register 2 (BOOTCFG2) 8 RW 00h
3.1.2 Chip ID1 register (CHIPID1)
Offset
Register Offset
CHIPID1 0h
NXP Semiconductors
QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021
User Guide 30 / 44