NXP Semiconductors S32G2 User Manual

S32G2 Vehicle Network Processor - Clock
Configuration Guide
by: NXP Semiconductors
1. Introduction
NXP’s S32G2 is a family of high-performance
vehicle network processors that combines Controller
Area Network (CAN), Local Interconnect Network
(LIN), and FlexRay networking with high-data-rate
Ethernet networking. It also combines a functional
safe-core infrastructure with MPU cores and includes
high-level security features.
S32G2 supports multiple clock sources for clock
generation:
• Fast Internal RC Oscillator (FIRC) (48 MHz)
• Slow Internal RC Oscillator (SIRC) (32 KHz)
• Fast External Crystal Oscillator (FXOSC) (20
– 40 MHz)
• Phase-Locked Loops (PLLs)
• Digital Frequency Synthesizer (DFS) modules
This application note is intended to provide the user
values for commonly used PLL/DFS configurations.
This document is accompanied with an attached clock
configurator - S32G2_Clock_Configurator.xlsx. The
calculator simplifies the clock configuration process
by helping user find the recommended and validated
values of PLL parameters (MFI, MFN and DIV), DFS
parameters (MFI and MFN), MC_CGM parameters
NXP Semiconductors
Document Number: AN13354
Application Notes
Rev. 1
,
11/2021
Contents
1. Introduction .................................................................... 1
2. PLL ................................................................................ 2
3. DFS ................................................................................ 4
4. Clock calculator design ................................................... 6
4.1 Options tab ........................................................... 6
4.2 Configuration tab.................................................. 7
4.3 Spread spectrum tab.............................................. 8
4.4 Clock calculator key considerations....................... 9
5. Spread Spectrum ........................................................... 10
5.1 Frequency modulation programming ................... 10
5.2 Spread Spectrum Considerations ......................... 11
5.3 Example code ..................................................... 12
6 Clock Configuration using S32DS Clocks Tool .............. 13
7 References .................................................................... 15

NXP Semiconductors S32G2 Specifications

General

Brand	NXP Semiconductors
Model	S32G2
Category	Computer Hardware
Language	English

Summary

Introduction to S32G2 Clock Configuration

Phase-Locked Loops (PLLs)

CORE PLL Configuration

Details configurations for the CORE PLL.

PERIPH_PLL Configuration

Details configurations for the PERIPH_PLL.

ACCEL_PLL Configuration

Details configurations for the ACCEL_PLL.

DDR_PLL Configuration

Details configurations for the DDR_PLL.

Digital Frequency Synthesizer (DFS)

CORE DFS Configuration

Details configurations for the CORE DFS.

PERIPH DFS Configuration

Details configurations for the PERIPH DFS.

Clock Calculator Design

Options Tab Interface

Interface for selecting FXOSC, RDIV, SSCG, and clock sources.

Configuration Tab Details

Provides PLL, DFS, and MC_CGM parameter values based on selections.

Spread Spectrum Tab Functionality

Calculates STEPNO and STEPSIZE for modulation depth and frequency.

Key Considerations for Clock Calculator

Important notes on RDIV, target frequency updates, and parameter ranges.

Spread Spectrum Clocking

Frequency Modulation Programming

Calculates STEPNO and STEPSIZE using specific formulas.

Spread Spectrum Considerations

Adherence to PLL VCO and modulation frequency specifications.

Modulation Depth Conditions

Conditions for modulation depth when center-spread SSCG is enabled.

Example Configuration

Illustrates configuring modulation frequency and depth with an example.

S32DS Clocks Tool Usage

References and Related Documents