Clock calculator design
S32G2 Vehicle Network Processor - Clock Configuration Guide, Rev. 1, 11/2021
8 NXP Semiconductors
As an example if the user selects the clock source for CAN_PE_CLK as PLL and 40 MHz as the target
frequency with RDIV and FXOSC value as 1 and 40 MHz respectively, the configuration tab provides
the values for clocking parameters as shown in the following image.
Figure 10. Configurations as per the selected parameters
4.3 Spread spectrum tab
With the help of this tab user can calculate values for STEPNO and STEPSIZE to program the
modulation depth and the modulation frequency.
The calculator takes the below input parameters:
1. VCO frequency with SSCG disabled
2. Reference frequency
3. RDIV
4. Modulation frequency
5. Modulation depth
User needs to enter the value for VCO frequency with SSCG disabled, modulation frequency and
modulation depth and select reference frequency and RDIV from the drop down list.
An example to calculate STEPNO and STEPSIZE for the CORE_PLL is shown below.
Figure 11. Spread spectrum tab
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