NXP Semiconductors S32G2 - Clock Calculator Design; Options Tab Interface

Clock calculator design
S32G2 Vehicle Network Processor - Clock Configuration Guide, Rev. 1, 11/2021
6 NXP Semiconductors
4. Clock calculator design
The S32G2 clock configurator is in the form of an interactive Microsoft Excel spreadsheet organized in
multiple tabs as explained in below sub-sections.
4.1 Options tab
The options tab provides an interface to select the following:
1. FXOSC frequency
Figure 3. Selecting FXOSC frequency
2. RDIV – RDIV is selected individually for each PLL : CORE_PLL, PERIPH_PLL,
ACCEL_PLL, DDR_PLL.
Figure 4. Selecting RDIV value
RDIV must be selected to ensure that the input frequency of each PLL is between 20 – 40 MHz.
3. Option to enable/disable SSCG for CORE_PLL, ACCEL_PLL and DDR_PLL.
Figure 5. Enabling/Disabling SSCG
4. Clock Source – Select the clock source.
Figure 6. Selecting the clock source