NXP Semiconductors S32G2 - Key Considerations for Clock Calculator

Clock calculator design
S32G2 Vehicle Network Processor - Clock Configuration Guide, Rev. 1, 11/2021
NXP Semiconductors 9
4.4 Clock calculator key considerations
1. RDIV – User must ensure that RDIV value remains in range when selecting or changing a
FXOSC frequency and manually update the RDIV value such that an invalid option is not
selected for the FXOSC frequency.
As an example, if the initial values for FXOSC and RDIV are selected as 40 MHz and 2
respectively and the user update the FXOSC frequency to 20 MHz, the RDIV block turns pink to
indicate the RDIV holds an invalid option for the selected FXOSC frequency. Therefore, the user
must correct the RDIV value in case the FXOSC frequency is updated.
Figure 12. Invalid RDIV error
Same precaution needs to be taken care while updating the FXOSC frequency in Spread
Spectrum tab.
2. Target frequency – As explained above, caution needs to be exercised while enabling or
disabling the SSCG mode. User should manually update the frequency when SSCG mode is
updated.
As an example, if Spread Spectrum is enabled for DDR_PLL and DDR_CLK is selected as 794
MHz and the user disables the spread spectrum, the F
DDR_CLK
block turns pink to indicate user to
update the F
DDR_CLK
from the list of frequencies in SSCG disabled mode.
Figure 13. Frequency update error
3. In the Spread Spectrum tab, user must ensure that the specified value for VCO frequency with
SSCG disabled, Modulation frequency and Modulation depth are within range as specified in
section Spread Spectrum Considerations.
Any invalid value selection leads to the specified parameter block turning pink. User must adjust
the value of specified parameter to be within range.