NXP Semiconductors S32G2 - Phase-Locked Loops (PLLs); CORE PLL Configuration; PERIPH_PLL Configuration; ACCEL_PLL Configuration

PLL
S32G2 Vehicle Network Processor - Clock Configuration Guide, Rev. 1, 11/2021
2 NXP Semiconductors
(SELCTL and DIV) to achieve the target clock frequency along with the calculation of STEPNO and
STEPSIZE for programming modulation depth and modulation frequency.
This document complements the S32G2 Reference Manual
1
and S32G2 Data Sheet
2
. Readers are
advised to read through “Clocking” chapter from S32G2 Reference Manual
1
before further diving into
this document.
The following table shows the abbreviations used throughout the document.
Table1. Acronyms and abbreviations
Abbreviation
Explanation
DFS
Digital Frequency Synthesizer
EMI
Electromagnetic Interference
FIRC
Fast Internal RC Oscillator
f
MOD
Modulation Frequency
f
PLL_VCO
PLL VCO frequency with SSCG enabled
f
REF
PLL Reference Clock
FXOSC
Fast External Crystal Oscillator
LDF
Loop Division Factor
MD
Modulation Depth
PLL
Phase Locked Loop
SSCG
Spread Spectrum Clock Generation
2. PLL
The document provides the coherent values for the following PLLs:
1. CORE_PLL
2. PERIPH_PLL
3. ACCEL_PLL
4. DDR_PLL