NXP Semiconductors S32G2 - Page 3

PLL
S32G2 Vehicle Network Processor - Clock Configuration Guide, Rev. 1, 11/2021
NXP Semiconductors 3
Figure 1. PLL block diagram
The user need to configure the value for below parameters to achieve the target frequencies for
PLL_VCO and PLL_PHIn.
1. Reference clock : Clock sources for the PLLs can either be the 20 – 40 MHz FXOSC or 48 MHz
FIRC. During boot, FIRC_CLK is used as the default PLL reference clock. After boot, the PLL
reference must be changed to FXOSC_CLK. Ensure that PLLCLKMUX[REFCLKSEL] is
selected accordingly.
RDIV : PLL input reference clock frequency after pre-divider should be between 20 – 40 MHz,
therefore the valid values for RDIV are shown in the following table.
Table2. RDIV values
Frequency
RDIV
FXOSC – 20 MHz
1
FXOSC – 24 MHz
1
FXOSC – 40 MHz
1 or 2
FIRC – 48 MHz
2