NXP Semiconductors QorIQ T2080 - Clocks

Golden finger
PEX4_RST_N
GND
Push-Button
MAX811S
(Power-on RST)
PWR_RST_N
COP_SRST_N
T2080
COP_ITF
T2080
HESET_REQ_N
HRSET_N
PORESET_N
C293
COP_ITF
C290_COP_HRST_N
C290_COP_SRST_N
C290_HESET_REQ_N
C290_HRSET_N
C293
C290 Reset
Logic
T2080
Reset
Source
select
RST_CTL
DDR_RSTN
NOR
FLASH
NOR_RSTN
PEX4S_RST
PEX SLOT
EDC_RST_N
CS4315
DVI_RST_N
EC1_RST_N
RGMII
GE PHY1
Soft reset register
RSTCON1 & RSTCON2
SW_RST
7
CPLD
COP_HRST_N
6
5
4
3
2
1
0
EC2_RST_N
RGMII
GE PHY2
DDR3/
DDR3L
10GBASET
PHY
AQR113C
10GBASET
PHY
AQR113C
DVI_RST_N
Figure 4. Reset architecture
2.4 Clocks
The clock circuitry provides clocks for the processor, for:
• SYSCLK
• DDRCLK (single-ended and differential)
• SerDes clocks
• Ethernet clocks
• USB clock
The architecture of the clock section is shown in the diagram below.
NXP Semiconductors
Architecture
QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021
User Guide 12 / 44