3.1.10 SFP+ control and status register (SFPCSR)
Offset
Register Offset
SFPCSR 14h
Diagram
Bits
0 1 2 3 4 5 6 7
R SFP1_DET
SFP1_TX...
SFP1_RX... SFP1_TX... SFP2_DET
SFP2_TX...
SFP2_RX... SFP2_TX...
W
Reset
u 0 u u u 0 u u
Fields
Field Function
0
SFP1_DET
SFP1_DET
0: SFP+1 module not inserted
1: SFP+1 module inserted
1
SFP1_TXDIS
SFP1_TXDIS
0: SFP+1 TX enable
1: SFP+1 TX disable
2
SFP1_RXLOS
SFP1_RXLOS
0: SFP+1 RX LOS logic 0
1: SFP+1 RX LOS logic 1(some SFP+ used as RXSD)
3
SFP1_TXFAIL
SFP1_TXFAIL
0: SFP+1 TX FAIL not occurs
SFP+1 TX FAIL occurs
4
SFP2_DET
SFP2_DET
0: SFP+2 module not inserted
1: SFP+2 module inserted
5
SFP2_TXDIS
SFP2_TXDIS
0: SFP+2 TX enable
1: SFP+2 TX disable
6 SFP2_RXLOS
Table continues on the next page...
NXP Semiconductors
CPLD Specification
QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021
User Guide 37 / 44