NXP Semiconductors QorIQ T2080 - Flash Control and Status Register (FLHCSR)

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Field Function
1: Writing logic 1 generates 10GBase-T PHY (AQR113C) reset# signal; this bit can auto clear.
7
PEX_RST
PEX_RST
0: No reset occurs
1: Writing logic 1 generates PCIe x4 slot reset# signal; this bit can auto clear.
3.1.7 Flash control and status register (FLHCSR)
Offset
Register Offset
FLHCSR 11h
Diagram
Bits
0 1 2 3 4 5 6 7
R BOOT_SEL
BANK_OR
SW_BANK... SW_BANK... SW_BANK...
BANK_SE... BANK_SE... BANK_SE...
W
Reset
u 0 u u u 0 0 0
Fields
Field Function
0
BOOT_SEL
BOOT_SEL
0: Boot from 16-bit NOR flash.
1: Boot from 8-bit NAND flash.
1
BANK_OR
BANK_OR
0: NOR flash bank select from CPLD override disable.
1: NOR flash bank select from CPLD override enable.
2
SW_BANK_SEL
0
SW_BANK_SEL0
0: NOR flash bank select bit0 of switch status is 0.
1: NOR flash bank select bit0 of switch status is 1.
3
SW_BANK_SEL
1
SW_BANK_SEL1
0: NOR flash bank select bit1 of switch status is 0.
1: NOR flash bank select bit1 of switch status is 1.
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NXP Semiconductors
CPLD Specification
QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021
User Guide 34 / 44