NXP Semiconductors QorIQ T2080 - DDR

OSC-66.66MHz
OSC-133.33MHz
OSC-24MHz
25MHz
ICS843002
Golden finger
EDC_REFCLK_P/N(156.25MHz)
SD1_REFCLK1_P/N(156.25MHz)
PEX4_REFCLK_P/N(100MHz)
PI3PCIE3212
CS4315
USB_REFCLK(24MHz)
DDRCLK(133.33MHz)
SYSCLK(66.66MHz)
T2080
SD1_REFCLK1_P/N
SD1_REFCLK2_P/N
SD2_REFCLK1_P/N
SD2_REFCLK2_P/N
P E X S L O T
C293
SD1_REFCLK2_P/N(100MHz)
PEX_CLK_P/N(100MHz)
IDT9FGV0641
SD2_REFCLK1_P/N(100MHz)
C290_SYSCLK (66.66MHz)
OSC-66.66MHz
SD2_REFCLK2_P/N(100M)
PEX4S_REFCLK_P/N(100M)
C290_SD_REFCLK_P/N(100M)
25MHz
Figure 5. Clock architecture
2.5 DDR
The T2080RDB-PC supports high-speed DRAM, with an SODIM socket, featuring single, dual, and quad-rank support. The
memory interface includes the necessary termination and I/O power and is routed to achieve maximum performance of the
memory bus, as shown in the diagram below.
NXP Semiconductors
Architecture
QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021
User Guide 13 / 44