NXP Semiconductors QorIQ T2080 - Reset Control Register (RSTCON)

3.1.6 Reset control register (RSTCON)
Offset
Register Offset
RSTCON 10h
Diagram
Bits
0 1 2 3 4 5 6 7
R SW_RST C293_RST
Reserved
EC1_RST EC2_RST EDC_RST XGT_RST PEX_RST
W W1C W1C W1C W1C W1C W1C W1C
Reset
u u u u u u u u
Fields
Field Function
0
SW_RST
SW_RST
0: No reset occurs.
1: Writing logic 1 generates whole board reset# signal; this bit can auto clear.
1
C293_RST
C293_RST
0: No reset occurs.
1: Writing logic 1 generates C293 Coprocessor reset# signal; this bit can auto clear.
2
—
-
3
EC1_RST
EC1_RST
0: No reset occurs.
1: Writing logic 1 generates RGMII PHY1 (RTL82111E-VB) reset# signal; this bit can auto clear.
4
EC2_RST
EC2_RST
0: No reset occurs.
1: Writing logic 1 generates RGMII PHY2 (RTL82111E-VB) reset# signal; this bit can auto clear.
5
EDC_RST
EDC_RST
0: No reset occurs.
1: Writing logic 1 generates 10GEDC PHY(CS4315) reset# signal; this bit can auto clear.
6
XGT_RST
XGT_RST
0: No reset occurs.
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NXP Semiconductors
CPLD Specification
QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021
User Guide 33 / 44