NXP Semiconductors QorIQ T2080 - SerDes Port

IV35
187Ohm
187Ohm
DDR_DQ[0:63]
DDR_ECC[0:7]
DDR_MA[0:15]
DDR_MDQS[0:8]
DDR_MDM[0:8]
DDR_MBA[0:2]
DDR_MDOT[0:1],DDR_MAPAR_OUT,DDR_MPAR_ERR
DDR_MCS[0:3]
DDR_MCK_P[0:1]_P/N
DDR_CAS,DDR_RAS,DDR_WE
DDR_MCKE[0:1]
IV35
DDR_RST_N
(CPLD)
I2C1_SCL,I2C1_SDA
MV_REF
VTT
IV35
(SPD_ADDR=0X51)
DDR3 SODIMM SOCKET
DIMM
T2080
DI_MDICI
DI_MDICO
IR3475
TPS
51200
Figure 6. Memory interface
2.6 SerDes port
The T2080 SerDes block provides 16 high-speed serial communication lanes, supporting various protocols, including:
• SGMII 1.25 / 3.125 Gbit/s
• PCI Express (PEX) Gen 1 1X / 2X / 4X 2.5 Gbit/s
• PCI Express (PEX) Gen 2 1X / 2X / 4X 5 Gbit/s
• SATA 1X 1.5 / 3 Gbit/s
The T2080 additionally supports these protocols:
• PCI Express (PEX) Gen 3 1X 8 Gbit/s
• XFI 1X 10.3125 Gbit/s
An overview of the SerDes protocols, which are supported on the T2080RDB, is shown in the table below.
NXP Semiconductors
Architecture
QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021
User Guide 14 / 44