Table continued from the previous page...
Field Function
1: PCIe x4 card present
7
TEST_SEL_N
TEST_SEL_N
0: TEST_SEL_N pin status is 0
1: TEST_SEL_N pin status is 1
3.1.12 Boot configuration override register (BOOTOR)
Offset
Register Offset
BOOTOR 16h
Diagram
Bits
0 1 2 3 4 5 6 7
R
Reserved BOOT_OR
W
Reset
0 0 0 0 0 0 0 0
Fields
Field Function
0-6
—
-
7
BOOT_OR
BOOT_OR
0: Boot configuration from CPLD overrides disable
1: Boot configuration from CPLD overrides enable
3.1.13 Boot configuration register 1 (BOOTCFG1)
Offset
Register Offset
BOOTCFG1 17h
NXP Semiconductors
CPLD Specification
QorIQ T2080 Reference Design Board (T2080RDB-PC) User Guide, Rev. 1, 08/2021
User Guide 39 / 44