GENERAL FEATURES
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The cache memory is a 8K bytes, 16 bytes line size, four-way
set associative configuration. The hit rate of this configuration is much
better than 32K bytes two-way set associative external cache because a
four-way set associative architecture provides better performance in a
multitasking and multi-processor environment.
Bus snooping feature keeps the cache memory consistent with
the main memory. When an external processor overwrites the content in
the main memory, the corresponding data in the internal cache memory
will be invalidated and will be fetched from main memory when CPU
reads this data.
If a read miss occurs, the CPU will initiate a burst mode read
operation. In burst mode read operation, CPU performs four successive
read operations each of which takes only one cycle. Total 128 bits data
are fetched into the CPU's internal cache. Since burst mode read
operation is very fast, the traffic of the CPU bus is greatly reduced and
the bus is available to other bus masters, such as DMA controller.
Reading 128 bits data into CPU will take some times. In order
to reduce the delay, the internal cache controller works parallel with
CPU. It fetches the data needed by CPU for the present operation and
the CPU read cycle is terminated. Then the other data are read into the
internal cache memory while CPU is doing something else. This
arrangement permits the CPU to run at zero wait state.
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