Onkyo TX-7230 - PLL Tuned Circuit; Frequency Indicator Circuit

5. PLL tuned circuit
FM local fo
Prescaler
oscillator
| circult 1/30 or 1/32
AM tocal 39:
oscillator
circurt
“al PSC
Swallow
counter
fo selector divider
_7.2MHz
crystal
oscillator
FM/AM Programmable| ft [Phase
fr Reference
frequency
comparator divider
reas oe cal
|
+
Low pass Eo
filter controler LSI
(fig. 6)
PSC
OUT 1
2) OUT 2
(fig 7) TO6104P (Prescaler)
A block diagram of the tuned circuit of the PLL is shown in
figer 6.
Operation during AM reception
The reception frequency is applied to the programmable
divider where it is divided to 1/N and output as fv. This is
applied to the phase comparator where it is comparated
with frequency reference fr (9kHz for G/W model and
10kHz for D model). If fr and fv differ, Eo equal to the dif-
ference in frequency is output. Since error output Eo is a
pulse waveform, it is passed through the low pass filter to
change it into DC voltage Vo, which is applied to the varia-
ble capacitor diode in the front end to change the reception
frequency. This continues until fv and fr are the same and
Eo=0.
Operation during FM reception
The pulse swallow method is used in the prescaler of
this unit. In this type of prescaler, a supplementary number
6. Frequency indicator circuit
al bicl di el fl gi a2b2¢2 d2e2 f2 g2 a3 b3 c3 d3 e3 13 g3
SEVEN SEGMENT DRIVER ISEVEN SEGMENT ORIVER
SEVEN SEGMENT ORIVER
Binary to BCD and IF OFFSET ROM
(fig. 8) TDG301AP block diagram
(changed according to the program code input) and the
divided reception frequency from the prescaler are com-
bined in the control counter and the prescaler’s division
factor is switched 1/30 or 1/32 according to external
control (1/32 when the PSC terminal is “H” and 1/30 when
it is “L”).
The station oscillator frequency is applied ot the program-
mable divider, but the programmable divider has en upper
frequency limit of only 30MHz, so the pulse swallow-type
prescaler, which can be used up to 150 MHz, is inserted for
division to 1/Np;
The signal is applied to the programmable divider and
divided to 1/N. The result is compared with a 25kHz
frequency reference in the phase detector and the error
is output as Eo until a match is obtained as in AM opera-
tion.