6 RX3i Redundancy Memory Xchange Module
GFK-2511H
RX3i CMX/RMX does not disable
transmitter when the CPU goes to
Stop/Halt mode.
For IC695CMX128 and IC695RMX128 modules not used as
redundancy links, the automatic transmitter disable feature
currently does not work correctly when a controller goes to
Stop/Halt mode. When the CPU goes to Stop/Halt mode or fails
and the automatic transmitter disable feature is enabled, the fiber
optic transmitter should be turned off, breaking the reflective
memory link. When the feature is disabled, the transmitter remains
ON and the reflective memory link will not be broken.
If this feature is enabled, the automatic transmitter disable feature
does not work when the CPU goes into Stop/Halt mode (such as
after a software watchdog trip or multi-bit ECC error detection)
leaving the fiber optic transmitter ON. The fiber optic transmitter is
properly disabled if the CPU fails or is lost (for instance the CPU
hardware is removed, the CPU experiences a hardware watchdog
event, or displays a blink code such as a page fault).
This user-configurable feature is enabled by default. The feature
may be disabled by clearing bit 12 with a BUS_WRITE to region 3,
offset 0x440.
Parity error received after extended run
on RMX module.
Infrequently, if parity is enabled on the RMX128 module when it is
not used as a Redundancy link, the module may intermittently
report a false parity error, although the associated data is valid.
The problem is more likely to occur when the same memory
locations are simultaneously and constantly accessed from both
the network and the RX3i backplane side.
The LCSR status bit is not turning ON
after LISR turns ON when Interrupt (Sync
Loss) is generated.
When a sync loss condition is detected the LISR bit is latched ON
but the LCSR sync loss bit is not latched ON (i.e. it remains OFF).
To check the sync loss status, monitor the sync loss bit in the LISR
register instead of the LCSR sync loss bit.
SVC_REQ 17 is not supported
SVC_REQ 17 is not supported to mask or unmask module
interrupts on RX3i CPUs. There is currently no way to identify
which module interrupt should be masked on RX3i. For RX7i this
was handled by a table of values, but this table of values is invalid
on RX3i. Instead the customer should simply turn off interrupts
using the normal interrupt disabling mechanism as described in the
user's manual.
Operational Notes
To prevent continuous interrupts when the Bad Data Interrupt is
enabled, you may want to temporarily set bit 8 in the LIER to 0
when a sync loss condition is detected. If your application is also
using the Sync Loss Interrupt, you may also want to temporarily set
bit 11 in the LIER to zero when the sync loss condition is detected.
You can then re-enable the Bad Data Interrupt (and Sync Loss
Interrupt if it was also disabled) when the sync loss condition has
been corrected.
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