Panasonic DMP-BD60GN - Sound and Display Settings; Sound Output Configuration

S-5
S3.3. Timer Block Diagram
REMOCON
27
1
M
DP7001
DISPLAY
TIMER
SG1
SG1-SG16
GR1-GR7
P1
F+
F+
F-
F-
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
7G
6G
5G 4G 3G
2G
1G
SG16
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
6
29
GR7
GR1
36
42
8 9 10 11 12 137
XN +4V
FRONT P.C.B.
OPEN SW P.C.B.
REGULATOR
BLOCK SECTION
TO DIGITAL P.C.B.
REGULATOR
BLOCK SECTION
FROM DIGITAL P.C.B.
Q1101,D1113
REGULATOR
QR57006,
QR57007
LED
DRIVE
P1102P58001
14 1
S7551
(RESET)
IC57005
OUT VDD
X SW+13V
DR P FAIL L
QR7003,
QR7004
Q7001,
QR7001
FAN LOCK
JC P ON H
JC P ON H
VREF
VDD(3.3V)
TUOVNIV
ON: GND
Q7003
X SW+3.3V
DIN
CLK
STB
IC7001
(DISPLAY/LED DRIVE)
P SAVE L
IC57001
(TIMER)
IR7201
SYS PFAIL L
PW GOOD H
10MHz OUT
10MHz IN
FAN DC
FL ON H
TBUS TXD
DR P ON H
DR P ON H
P STANDBY H
H
P STANDBY H
FL TXD
FL CLK
FL CS L
KEY IN3 POWER
KEY IN2
(MAIN CLK)
10MHz
X57001
FAN MOTOR
(FAN MOTOR SWITCH)
Q57001
X SW+13V
IC57004
(FAN MOTOR DRIVE)
A OUTA+IN
SENSOR
REMOTE CTL.
VEE
POWER SW P.C.B.
DIGITAL P.C.B.
POWER P.C.B.
POWER
XN +4V
D57001
(1/2)
D57001
(1/2)
D1108
T1001
D1107
S7204 S7206
PAUSE STOP
S7581
OPEN CLOSE
D7201
CENTER
P7201
P57001
8
P7201
P57001
9
PJ7551
PJ7204
1
P7201
P57001
7
S7202
PLAY
6
7
3
KEY IN 1 OP CL
PJ7581
PJ7203
1
1
2
21
20
18
P7201P57001
P7201P57001
P7201P57001
4
3
2
P7001P7202
P7001P7202
P7001P7202
3
4
5
CENTER LED
54
9
8
7
DOUT
6
30
VDD
13
VDD
43
1
P7201
P57001
P7201
P57001
6
10
X SW+3.3V
2
IP1102
IC PROTECTOR
2113
17
11
10
IP1101
IC PROTECTOR
2
9
8
53
14
8
45
1
POWER
SUPPLY
FIP
CONTROL
21
59
(PEAKS-PRO2)
IC51001
CSBPTM
15
13
OUT 54 VDD
P7003
1
P1102
12
P58001
3
P1102
13
P7003
3
P58001
2
P58001P1102
3 12
62
47
58
37
43
49
42
POWER P.C.B.
TO
32
31
1
2
IC57002
(RESET)
IC1102
(REG.)
RESET
DMP-BD60GN/GA/GC/GZ/PU,
DMP-BD80GN
Timer Block Diagram
U34
TBUS RXD
CSBMTP
16
V32
TBUS CLK
CSCLK
17
U33
QR57003,
QR57004, Q57004
BUFFER
FOR BD80 ONLY
FOR BD80 ONLY
P SAVE L
FL ON H
P1102P58001
13 2
POWER P.C.B.
TO