Panasonic TH-L42S10M - 1.3. KM03 Chasis Block Diagram

TH-L42S10M
6
1.3. KM03 Chasis Block Diagram
TUNER
PWB
Hong Kong Digital
FE
S(5 or 6)/3.3
SDRAM
TUNER
TS
Parallel
ON Fix (Hard)
S5V
CI
P
O
W
ER
-
SW
P>CI_POWER_ON P<CI_OCP
S3.3/1.8/1.2
M_SND
S5
M3.3
S3.3
S3.3
S3.3
AV
-
SW
R2A11014FT
Video
Audio
SW
SLV[90]
HD/VD/FBK
MUTE
STB_XRST
5VS/STB5/S5/DTV12
S3.3
10MHz
S3.3
S3.3
S3.3/S5
S3.3
S3.3/S5
P> FE_SW
Opt
Digital OUT
CVBS
S3.3/S1.8
S9/S5
HP
AMP
MAIN
AMP
AV-OUT
MONITOR
OUT
CVBS
L/R
HP_OUT
L/R
AV-IN
YUV
CVBS/S
L/R
YUV
CVBS/S
L/R
CVBS
L/R
PC
RGB
HS/VS
ADV7470
SLV[40,etc]
HDMI-Rx *4
AD-IN
Y/CVBS
Pb/C Pr
RGB_CVBS
SOY
RGB_FB
PC_HS
PC_VS
INT
ADV_RESET
SIF
S3.3/S1.8
HDMI
G>HPD
G<5V_DET
G<CEC
AV_L/R
MONITOR_OUT
L/R
AM
TV_L/R
L/R
L/R
L/R
MAIN
VIDEO
TU-CVBS
FE
WJCE6553
SLV[1E]
S5/S30
TUNER
SW1/2
mono
SIF
IF AGC
IF
PWM_OUT *1
Opt
CI
Card
TS
SW
3.3-5V
Level
Shift
TS
Buffer
CI
ASIC
#WE/#RE
#IOWR/#IORD #REG Buffer Ctrl
#CD #IREQ #WAIT
Peaks-AVC
31mm
IIC0
IIC1
IIC2
IIC3
G> AUDIO_XRST
IRQ3
74.25MHz
27MHz
27MHz
12MHz → nonuse
25MHz → for LAN9118
IC
S
CLKGEN
w/t
VCXO
S1.8
TS
Serial
TS
Parallel
HSDIN
VI1CLKOUT
RGB 30bit
H,V,CLK
A
P
ort
Video DAC
IECOUT
Audio
Discription
I2S
I2S
RTL8100
CL-LF
Reset
25MHz
From CLKGEN
Ether
C
onne
c
ter
ADDR &DATA
32bit +4bit
EE
P
1k
S3.3
A
na
l
og
A
S
I
C
BD8651
GenX8
SLV[70]
SBO2 SBI2
EEPWP
IIC_1
SD-BOOT
STB3.3
EEP 8k
S
L
V
[
A
0}
STB3.3
Su
p
port c
a
r
d
c
o
nnect or
NACE,CE1 CLE1 ALE1 WE1
WP BYRE1
NOR Flas
h
2
5
6M
bi
t
XRST
CS0
S3.3
STB3.3
OUT
RESET
HP
G> ADV_XRST
LVDS-1st
LVDS-2nd
USB-IF
TS Parallel
PWMA PWMK
LOSD
G> DTV_VOUTENB
AVC System MW: NONE SD: ONBOARD
SD-IF
BLUE-LED: NONE
S3.3
E
E
P
16
k
S
L
V[A0}
S3.3
TE
MP SENSE
S
LV[
A
0}
RMT/ KEY
V-PWB
STB3.3/S5
G> SD_LED_ON
G> G_LED_ON
G> R_LED_ON
G> ACTIVE_STBY_LED_ON
G< RMIN G< AI_SENSOR
G< KEY1
PCI BUS /VOUT
IS0
CH0
FS
NONE
OVP SOS G>MON_MUTE
G>SP_HP_MUTE
AMP/HP_MUTE
MONITOROUT_MUTE
G< TV_SOS
P> CI_XRST
P> EEPROM_WP
G> EEPROM_WP
Peaks_XRST
Peaks POWER_DET
RESET
POWER_DET
G>DTV_XRST
G>SW_OFF_DET
DDR2
800MHz
DDR2
800MHz
CPU BUS
ADDRESS EA[25:24], EA[7:0]
DATA ED[15:0]
B
po
rt
/ ADDRESS EA[23:8]
YC 16bit
H,V,CLK
ADDRESS
EA[25:0]
DATA
ED[15:0]
ADDRESS
EA[7:1]
DATA
ED[7:0}
ADDRESS
CI_EA[15:1]
DATA
CI_ED[7:0]
5-3.3V
Level
Shift
P> XETS_CI
S3.3/S5
P> FE1_IRQ
P< FE_XRST
P> FE_IRQ P< FE_XRST
AMP/HP_MUTE
(G>SP_HP_MUTE)
MONITOROUT_MUTE
(G>MON_MUTE)
PWMA PWMK
G>PWM_POW_ON
G<INVERTER_SOS
LVDS Dual
PWM
ADIM
Filter
M9
LCD PANEL
G>INVERTER_ON G>PANEL_TEST_ON
PNL_VCC
ADV
IIC
ADAV
IIC
24.576MHz to ADAV Block
ADV CLK from ADAV MCLK out
ADAV
MCLK
ADV CLK
30MHz
30.4MHz
TS Serial
TS
Parallel
IIC_0
L/R
S
P
G<SOUND_SOS AMP/HP_MUTE
(G>SP_HP_MUTE)
SD-IF
NAND-IF
S3.3
NAND
F
las
h
DATA
ED[7:0]
XNFCE,XNFWE,XNFRE
NFALE,NFCLE,XNFWP
NANDRYBY
S3.3
SD
Card
EA[23:8] ED[15:0]
G> ADV_XRST
ADAV_RESET
PWM OUT *2
HP_OUT
PWM_READY
SPDIF_OUT
SPDIF_IN
DTV_I2S_IN
HDMI_I2S_SPDIF
OUT/IN